Control and interconnection system

• US 20070073908A1
• Filed: 09/23/2005
• Published: 03/29/2007
• Est. Priority Date: 09/23/2005
• Status: Active Grant

• Current Assignee: Joseph Gormley As Trustee Under The Joseph Gormley Trust Dated August 16 2010
• Original Assignee: Joseph Gormley
• Inventors: Gormley, Joseph
• Granted Patent: US 7,590,768 B2
• Time in Patent Office: Days
• US Class Current: 710/8
• CPC Class Codes: G05B 19/0421 Multiprocessor system

Abstract

A control and interconnection system for integrating a plurality of peripherals into a computer system comprises a system core for processing data, an input module adapted to couple signals from associated peripherals to the system core and an output module adapted to direct signals from the system core to corresponding peripherals. The system core includes a reconfigurable space having hardware for supporting reconfigurable hardware programming and memory for supporting reconfigurable software programming to offload at least a portion of peripheral processing requirements to the system core. The system core further provides a supervising processor that is configured to provide control information to identified peripherals as necessary to implement a customized overall configuration. The supervising processor further controls the allocation and configuration of the reconfigurable space into a plurality of independent information processing workspaces, where each information processing workspace supports hardware, software or both hardware and software.

Claims

1. A control and interconnection system for integrating a plurality of peripherals into a computer system having a reconfigurable processing environment comprising:

a system core for processing data, an input module adapted to couple signals from associated peripherals to said system core and an output module adapted to direct signals from said system core to corresponding peripherals, wherein said system core comprises;

a reconfigurable space for offloading at least some peripheral processing requirements to said system core, said reconfigurable space having hardware for supporting reconfigurable hardware programming and memory for supporting reconfigurable software programming of peripheral-specific or application-specific functionalities that are not related to system core processes;

a supervising processor operatively configured to;

provide control information to at least one peripheral associated with said control and interconnection system to coordinate performance characteristics of multiple peripherals based upon at least one determined operating condition;

control the allocation of said reconfigurable space into a plurality of independent information processing workspaces, where each information processing workspace is defined by at least one of an allocated portion of said hardware for supporting reconfigurable hardware programming and an allocated portion of said memory for supporting reconfigurable software programming; and

control the configuration of each allocated information processing workspace based upon programming instructions that implement peripheral defined functionalities;

a general purpose processor for interaction with said memory of said reconfigurable space and for executing functions of said system core; and

a peripheral controller arranged to direct the flow of information in said control and interconnection system by communicating data between said input module, said output module, and at least one of said reconfigurable space and said general purpose processor, wherein select input signals at said input module are associated with their associated information processing workspace in said reconfigurable space of said system core.

2. The control and interconnection system according to claim 1, further comprising a logic plane for supporting said system core, a separate power board plane for providing power to said system core, a separate base wiring plane for supporting a plurality of connectors for coupling peripherals to said input and output modules and at least one flexible bus bar plane for bussing signals between said logic plane and said base wiring plane, and between said power board plane and said base wiring plane.

3. The control and interconnection system according to claim 2, wherein said power board plane further supplies power to at least one peripheral associated with said control and interconnection system.

4. The control and interconnection system according to claim 1 wherein said system core further comprises a data engine and a corresponding development library for supplying partially and/or completely defined building blocks to configure said information processing workspaces.

5. The control and interconnection system according to claim 1, further comprising a configuration library that interacts with said data engine to pass configuration data to at least one of said general purpose processor and said supervising processor.

6. The control and interconnection system according to claim 1, wherein:

said input module comprises reconfigurable hardware such that inputs of said input module can be rerouted to different paths within said system core; and

said output module comprises reconfigurable hardware such data paths from said system core can be rerouted to different outputs.

7. The control and interconnection system according to claim 1, wherein said at least one determined operating condition used by said supervising processor to provide control information to said at least one peripheral associated with said control and interconnection system to coordinate performance characteristics of multiple peripherals is based upon at least one of operator preference data, sensed operational conditions, inferred operational conditions, sensed environmental conditions and inferred environmental conditions.

8. A method of integrating a plurality of peripherals into a control and interconnection system having a reconfigurable processing environment comprising:

providing a system core for processing data having a reconfigurable processing environment;

providing an input module adapted to couple signals from associated peripherals to said system core and an output module adapted to direct signals from said system core to corresponding peripherals;

receiving a request to allocate an information processing workspace from said reconfigurable processing environment to implement peripheral specific processing of a first peripheral;

receiving associated with said first peripheral, programming instructions to configure said allocated information processing workspace with at least one of hardware and software configuration information;

allocating an unused portion of said reconfigurable processing environment for use by said first peripheral sufficient to implement said programming instructions if said programming instructions are properly authorized;

configuring said allocated information processing workspace based upon said programming instructions to perform at least one of function specific or peripheral specific applications; and

during operation, controlling interaction with said allocated information processing workspace to authorized peripherals.

9. The method according to claim 8, wherein said system core further comprises a mission configuration controller for:

providing configuration data to peripherals associated with said control and interconnection system to oversee integrated operation of said peripherals.

10. The method according to claim 9, further comprising dynamically modifying said configuration data during use based upon at least one of sensed environmental conditions, inferred environmental conditions, sensed operating conditions, inferred operating conditions and operator preference data.

11. The method according to claim 8, further comprising providing at least one template that allows associated peripherals to customize operator interaction with said control and interconnection system.

12. The method according to claim 8, further comprising providing a development library for constructing associated information processing workspaces so that associated peripherals can offload at least a portion of their hardware or software requirements to their corresponding information processing workspace by utilizing pre-configured building blocks.

13. The method according to claim 8, further comprising:

providing in said system core, a security and diagnostics processor for determining whether a configuration operates correctly based upon at least one of mission configuration settings identified by a mission configuration controller, configuration commands based upon driver settings and alternate parameters provided by a mode control monitor.

14. The method according to claim 8, further comprising providing in said system core a security processor configured to monitor access to said reconfigurable space so as to define information processing workspaces as at least one of:

globally accessible to all peripherals,

accessible to a predetermined class of peripherals,

restricted to select peripherals or

restricted for exclusive use by a select peripheral that requested the associated information processing workspace.

15. A control and interconnection system for integrating a plurality of peripherals into a computer system having a reconfigurable processing environment comprising:

a system core for processing data, an input module adapted to couple signals from associated peripherals to said system core and an output module adapted to direct signals from said system core to corresponding peripherals, wherein said system core comprises;

a reconfigurable space for offloading at least a portion of peripheral processing requirements to said system core, said reconfigurable space having hardware for supporting reconfigurable hardware programming and memory for supporting reconfigurable software programming of peripheral-specific or application-specific functionalities that are not related to system core processes;

a supervising processor configured to control the allocation and configuration of said reconfigurable space into a plurality of independent information processing workspaces, where each information processing workspace is defined by at least one of an allocated portion of said hardware for supporting reconfigurable hardware programming and an allocated portion of said memory for supporting reconfigurable software programming based upon programming instructions that implement peripheral defined functionalities,

a mission configuration control operatively configured to provide control information to at least one peripheral associated with said control and interconnection system to coordinate performance characteristics of multiple peripherals;

a mode control monitor operatively configured to dynamically modify said control information based upon at least one determined operating condition;

a general purpose processor for interaction with said memory of said reconfigurable space and for executing functions of said system core; and

a peripheral controller arranged to direct the flow of information in said control and interconnection system by communicating data between said input module, said output module, and at least one of said reconfigurable space and said general purpose processor, wherein select input signals at said input module are associated with their associated information processing workspace in said reconfigurable space of said system core.

16. The control and interconnection system according to claim 15, wherein said peripherals are arranged in a hierarchical grouping of classes and said supervising processor is further configured to oversee operating characteristics of each class based upon said at least one determined operating condition such that an overall configuration is customized.

17. The control and interconnection system according to claim 16, wherein said mode control monitor is configured to dynamically alter said at least one determined operating condition based upon at least one of entered preference data, sensed operational conditions, inferred operational conditions, sensed environmental conditions and inferred environmental conditions.

18. The control and interconnection system according to claim 16, wherein said hierarchical grouping of classes are defined by classes of vehicle components.

19. The control and interconnection system according to claim 16, wherein said hierarchical grouping of classes are defined by classes of home electronics components.

20. The control and interconnection system according to claim 15, wherein said input and said output modules communicate with associated peripherals over at least one of a direct connection or an indirect connection via an application appropriate bus.