Reliable computing with a many-core processor

• US 20070074011A1
• Filed: 09/28/2005
• Published: 03/29/2007
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Garver, Shu-Ling, Borkar, Shekhar, Hoskote, Yatin
• Granted Patent: US 7,412,353 B2
• Time in Patent Office: Days
• US Class Current: 712/227
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/1637 using additional compare functionality in one or some but not all of the redundant processing components
• CPC Class Codes: G06F 11/165 with continued operation after detection of the error
• CPC Class Codes: G06F 11/1695 which are operating with time diversity
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to embodiments of the disclosed subject matter, cores in a many-core processor may be periodically tested to obtain and/or refresh their dynamic profiles. The dynamic profile of a core may include information on its maximum operating frequency, power consumption, power leakage, functional correctness, and other parameters, as well as the trending information of these parameters. Once a dynamic profile has been created for each core, cores in a many-core processor may be grouped into different bins according to their characteristics. Based on dynamic profiles and the grouping information, the operating system (“OS”) or other software may allocate a task to those cores that are most suitable for the task. The interconnect fabric in the many-core processor may be reconfigured to ensure a high level of connectivity among the selected cores. Additionally, cores may be re-allocated and/or re-balanced to a task in response to changes in the environment.

Claims

1. A many-core processor, comprising:

multiple processing cores;

interconnect fabric;

at least one memory module, said multiple cores and said at least one memory module coupled to said interconnect fabric; and

a profiling module to dynamically profile characteristics of each core in said many-core processor.

2. The processor of claim 1, wherein said profiling module comprises:

a power consumption measuring module to periodically measure power consumption by each core in said many-core processor under different voltages and different speeds;

an operating speed measuring module to periodically measure the maximum speed of each core in said many-core processor under different voltages; and

a reliability tracking module to obtain reliability information of each core in said many-core processor based at least in part on said measured power consumption data and maximum speeds of each core in said many-core processor.

3. The processor of claim 2, further comprising at least one temperature sensor to measure temperature distribution and to identify hot spots across the die area of each core and said interconnect fabric in said many-core processor.

4. The processor of claim 3, wherein said reliability tracking module obtains trending information of said temperature distribution and said hot spots over time.

5. The processor of claim 2, further comprising a functional correctness checking module to check functional correctness of each core in said many-core processor.

6. The processor of claim 5, wherein said functional correctness checking module performs functional correctness checks in at least a coarse grain level.

7. The processor of claim 5, wherein said reliability tracking module obtains trending information of functional correctness of each core in said many-core processor over time.

8. The processor of claim 2, further comprising a controller to control and coordinate at least said power consumption measuring module, said operating speed measuring module, and said reliability tracking module in a process of dynamically profiling the characteristics of each core in said many-core processor.

9. A method for dynamically profiling characteristics of each core in a many-core processor, comprising:

periodically initiating a test for each core in said many-core processor;

measuring power consumption data of each core in said many-core processor during each test under different voltages and different operating speeds;

measuring the maximum operating speed of each core in said many-core processor during each test under different voltages; and

obtaining reliability information of each core in said many-core processor based at least in part on said power consumption data and said maximum operating speed obtained during each test.

10. The method of claim 9, further comprising:

measuring temperatures to obtain hot spots and temperature variation across the die area of each core and said interconnect fabric in said many-core processor; and

conducting functional correctness checks to obtain functional correctness information of each core in said many-core processor.

11. The method of claim 10, wherein said reliability information comprises trending information of said hot spots and temperature variation across the die area and said functional correctness information of each core in said many-core processor over time.

12. The method of claim 10, further comprising obtaining and storing a performance profile for each core in said many-core processor, said performance profile including at least one of said power consumption data, said maximum operating speed, said functional correctness information, said hot spots and temperature variation across the die area of each core, and trending information thereof for each core in said many-core processor.

13. A computing system, comprising:

a many-core processor, said processor including a profiling module to create a dynamic profile for each core in said processor; and

a task allocating module to receive a task and to allocate said task application to a first set of cores based at least in part on requirements of said task and said dynamic profile of each core in said processor.

14. The system of claim 13, wherein said processor further comprises a core binning module to use at least one characteristic of cores as a criterion to group cores in said processor into multiple bins based on said dynamic profile of each core, said multiple bins being used by said task allocating module to allocate said task to said first set of cores.

15. The system of claim 13, further comprising a performance and power manager to at least one of re-allocate said task to a second set of cores and re-balance said first set of cores in response to a changing condition, said second set of cores including at least one different core from said first set of cores.

16. The system of claim 15, further comprising a reconfigurator to reconfigure interconnects among at least one of said first set of cores and said second set of cores.

17. The system of claim 15, wherein said changing condition includes at least one of a changing condition of at least one core in said first set of cores and a changing environment.

18. A method for efficiently executing a task using a many-core processor, comprising:

receiving a task;

analyzing said task to determine requirements of said task;

allocating said task to a first set of cores in said many-core processor based on said requirements of said task; and

executing said task using said first set of cores.

19. The method of claim 18, further comprising grouping cores in said many-core processor into multiple bins based on a dynamic profile of each core, according to at least one characteristic of cores in said many-core processor.

20. The method of claim 18, further comprising at least one of re-allocating said task to a second set of cores and re-balancing said first set of cores in response to a changing condition, said second set of cores including at least one different core from said first set of cores.

21. The method of claim 20, wherein said changing condition including at least one of a changing condition of at least one core in said first set of cores and a changing environment.

22. The method of claim 20, further comprising reconfiguring interconnects among at least one of said first set of cores and said second set of cores.