EXTENDED INSTRUCTION SET FOR PACKET PROCESSING APPLICATIONS

• US 20070074014A1
• Filed: 09/12/2006
• Published: 03/29/2007
• Est. Priority Date: 02/08/2000
• Status: Abandoned Application

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Musoll, Enrique, Nemirovsky, Mario, Melvin, Stephen
• Application Number:
  US11/530,945
• Publication Number:
  US 20070074014A1
• Time in Patent Office: Days
• US Class Current: 712/300
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 47/621 Individual queue per connection or flow, e.g. per VC
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet

Abstract

A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of memory, a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets, a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and a portion thereof for managing selection and utilization of arithmetic and other context memory functions associated with data packet processing. The extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a streaming processor unit.

Claims

1-11. -11. (canceled)

12. A dynamic multi-streaming processor comprising:

a packet management component; and

a stream processing component, wherein said stream processing component is configured to operate independently from the packet management component;

wherein the packet management component is configured to manage packets received and processed by the stream processing component concurrent with packet processing by the stream processing component.

13. The processor as recited in claim 12, wherein in managing packets the packet management component is configured to:

manage memory allocation for packet storage;

upload packet header information from incoming packets into different contexts; and

maintain packet identifiers of packets currently in process.

14. The processor as recited in claim 12, further comprising circuitry configured to execute instructions of an instruction set that enables interaction between the packet management component and the stream processing component, said instruction set including a portion for managing memory allocations and de-allocations associated with enqueueing and dequeuing data packets.

15. The processor as recited in claim 12, further comprising circuitry configured to execute instructions of an instruction set that enables interaction between the packet management component and the stream processing component, said instruction set including a portion for managing selection and utilization of one or more arithmetic functions and other context memory functions associated with data packet processing.

16. The processor as recited in claim 15, wherein the portion for managing selection and utilization of one or more arithmetic functions and other context memory functions associated with data packet processing includes instructions for gathering information from memory for loading into a context, distributing information from a context into memory, selecting and accessing at least one addition function, and for selecting and accessing at least one subtraction function.

17. The processor as recited in claim 12, further comprising circuitry configured to execute instructions of an instruction set that enables interaction between the packet management component and the stream processing component, said instruction set including a portion for managing the use of multiple contexts dedicated to the processing of a single data packet.

18. The processor as recited in claim 17, wherein the portion for managing the use of multiple contexts includes an instruction for forcing nonuse of a context for a predefined period of time.

19. A method for use in a dynamic multi-streaming processor comprising a packet management component, and a stream processing component, wherein the stream processing component is configured to operate independently from the packet management component, the method comprising:

receiving packets for processing by the stream processing component; and

managing in the packet management component the received packets and packets being processed by the stream processing component concurrent with packet processing by the stream processing component.

20. The method as recited in claim 19, wherein in managing packets the method comprises:

managing memory allocation for packet storage;

uploading packet header information from incoming packets into different contexts; and

maintaining packet identifiers of packets currently in process.

21. The method as recited in claim 20, further comprising executing instructions of an instruction set that enable interaction between the packet management component and the stream processing component, said instruction set including a portion for managing memory allocations and de-allocations associated with enqueueing and dequeuing data packets.

22. The method as recited in claim 20, further comprising executing instructions of an instruction set that enable interaction between the packet management component and the stream processing component, said instruction set including a portion for managing selection and utilization of one or more arithmetic functions and other context memory functions associated with data packet processing.

23. The method as recited in claim 22, wherein the portion for managing selection and utilization of one or more arithmetic functions and other context memory functions associated with data packet processing includes instructions for gathering information from memory for loading into a context, distributing information from a context into memory, selecting and accessing at least one addition function, and for selecting and accessing at least one subtraction function.

24. The method as recited in claim 20, further comprising executing instructions of an instruction set that enables interaction between the packet management component and the stream processing component, said instruction set including a portion for managing the use of multiple contexts dedicated to the processing of a single data packet.

25. The method as recited in claim 24, wherein the portion for managing the use of multiple contexts includes an instruction for forcing nonuse of a context for a predefined period of time.

26. A system comprising:

an interface configured to transmit and receive packets;

an external packet memory; and

a dynamic multi-streaming processor coupled to the interface and the external memory, the processor comprising;

a packet management component; and

a stream processing component, wherein said stream processing component is configured to operate independently from the packet management component;

wherein the packet management component is configured to manage packets received and processed by the stream processing component concurrent with packet processing by the stream processing component.

27. The system as recited in claim 26, wherein in managing packets, the packet management component is configured to:

manage memory allocation for packet storage;

upload packet header information from incoming packets into different contexts; and

maintain packet identifiers of packets currently in process.

28. The system as recited in claim 27, wherein the packet management component further comprises a local packet memory, and wherein the packet management component is configured to utilize both the local packet memory and the external packet memory for storage of packet data.

29. The system as recited in claim 27, wherein the processor is further configured to execute instructions of an instruction set that enables interaction between the packet management component and the stream processing component, said instruction set including a portion for managing memory allocations and de-allocations associated with enqueueing and dequeuing data packets.

30. The system as recited in claim 27, wherein the processor is further configured to execute instructions of an instruction set that enables interaction between the packet management component and the stream processing component, said instruction set including a portion for managing selection and utilization of one or more arithmetic functions and other context memory functions associated with data packet processing.

31. The system as recited in claim 30, wherein the portion for managing selection and utilization of one or more arithmetic functions and other context memory functions associated with data packet processing includes instructions for gathering information from memory for loading into a context, distributing information from a context into memory, selecting and accessing at least one addition function, and for selecting and accessing at least one subtraction function.

32. The system as recited in claim 27, wherein the processor is further configured to execute instructions of an instruction set that enables interaction between the packet management component and the stream processing component, said instruction set including a portion for managing the use of multiple contexts dedicated to the processing of a single data packet.

33. The system as recited in claim 32, wherein the portion for managing the use of multiple contexts includes an instruction for forcing nonuse of a context for a predefined period of time.