NAND flash memory controller exporting and NAND interface

• US 20070074093A1
• Filed: 01/06/2006
• Published: 03/29/2007
• Est. Priority Date: 09/26/2005
• Status: Active Grant

• Current Assignee: Innovative Memory Systems, Inc. (Wi-LAN Inc.)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Lasser, Menahem
• Granted Patent: US 7,631,245 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS

Abstract

A NAND controller for interfacing between a host device and a flash memory device (e.g. a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed.

Claims

1. A controller for interfacing between a host device and a flash memory device fabricated on a flash die, the controller comprising:

a) electronic circuitry fabricated on a controller die, said controller die being distinct from the flash die;

b) a first interface for interfacing between said electronic circuitry and the flash memory device; and

c) a second interface for interfacing between the controller and the host device, wherein said second interface is a NAND interface.

2. The controller of claim 1 wherein said first interface is a NAND interface.

3. The controller of claim 1 further comprising:

d) an error correction module for providing error correction for data received through one of said first and second interface.

4. The controller of claim 1 further comprising:

d) at least one additional host-side interface for interfacing with the host device.

5. A data storage system comprising:

a) a flash memory device fabricated on a flash die; and

b) the controller of claim 1, said controller being operative to communicate with said flash memory device through said first interface.

6. The system of claim 5 further comprising:

c) a common packaging,

wherein said flash memory device and said controller are both provided within said common packaging.

7. The system of claim 5 further comprising:

c) separate respective packagings,

wherein each of said flash memory device and said controller is provided within a respective said packaging.

8. The system of claim 5 further comprising

c) a printed circuit board on which said flash memory device and said controller are mounted, wherein said flash die is directly mounted on said printed circuit board.

9. The system of claim 5 further comprising

c) a printed circuit board on which said flash memory device and said controller are mounted, wherein said controller die is directly mounted on said printed circuit board.

10. A data storage system comprising:

a) a host device;

b) a flash memory device fabricated on a flash die; and

c) the controller of claim 1 operative to communicate with both said flash memory device through said first interface and with said host device through said second interface.

11. A method of creating a data storage system, the method comprising:

a) providing a flash memory device fabricated on a flash die;

b) providing the flash controller of claim 1;

c) deploying said flash controller to said flash memory device such that said flash controller is operative to communicate with said flash memory device through said first interface.

12. The method of claim 11 further comprising:

d) packaging said flash controller and said flash memory device within a single package.

13. The method of claim 11 wherein said flash memory device and said flash controller reside within separate respective packages, and said deploying includes engaging said respective packages to each other.

14. The method of claim 11 further comprising

d) mounting said flash memory device and said controller onto a printed circuit board,

wherein said mounting includes directly mounting said flash memory die onto said printed circuit board.

15. The method of claim 11 further comprising

d) mounting said flash memory device and said controller onto a printed circuit board,

wherein said mounting includes directly mounting said controller die onto said printed circuit board.

16. The method of claim 11 further comprising:

d) deploying the data storage system to a host device such that said flash controller is operative to communicate with said host device through said second interface.

17. A method of writing data from a host device, the method comprising:

a) providing a flash memory device fabricated on a flash die and a controller fabricated on a controller die, said flash die being distinct from said controller die;

b) issuing a write command from the host device to the controller according to a NAND interface protocol; and

c) issuing a write command from the controller to the flash memory device according to a NAND interface protocol.

18. The method of claim 17 further comprising:

d) calculating parity bits by the controller.

19. A method of reading data to a host device, the method comprising:

a) providing a flash memory device fabricated on a flash die and a controller fabricated on a controller die, said flash die being distinct from said controller die;

b) issuing a read command from the host device to the controller according to a NAND interface protocol; and

c) issuing a read command from the controller to the flash memory device according to a NAND interface protocol.

20. The method of claim 19 further comprising:

d) retrieving the data from the flash memory device to the controller;

e) retrieving parity bits associated with said retrieved data from the flash memory device to the controller;

f) correcting said retrieved data according to said retrieved parity bits, thereby generating corrected data; and

g) retrieving said corrected data from the controller to the host device.