Method and apparatus for N‘packet level mesh protection

• US 20070074095A1
• Filed: 09/29/2005
• Published: 03/29/2007
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Langner, Paul
• Granted Patent: US 7,624,333 B2
• Time in Patent Office: Days
• US Class Current: 714/781
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0061 Error detection codes

Abstract

Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoding method is provided that assembles M-T data packets; appends a sequence number and a payload integrity check to each of the M-T data packets; and creates T protection packets having the sequence number and payload integrity check, wherein a payload for each of the T protection packets are formed from corresponding symbols in the M-T data packets. An error correction decoding method is also provided that receives a plurality of error-free packets and one or more packets having an error; and reconstructs the one or more packets having an error by applying block erasure decoding to said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode the received packets.

Claims

1. An error correction encoding method, comprising:

assembling M-T data packets;

appending a sequence number and a payload integrity check to each of said M-T data packets; and

creating T protection packets having said sequence number and payload integrity check, wherein a payload for each of said T protection packets are formed from corresponding symbols in said M-T data packets.

2. The method of claim 1, wherein said payload of said T protection packets is equal on a symbol-by-symbol basis to the check symbols of a block erasure code calculated over the corresponding symbols in said M-T packets.

3. The method of claim 1, wherein said payload integrity check is a cyclic redundancy check.

4. The method of claim 3, wherein said cyclic redundancy check is a CRC-32.

5. The method of claim 1, wherein said payload integrity check employs an error correcting code.

6. An error correction decoding method, comprising:

receiving a plurality of error-free packets and one or more packets having an error; and

reconstructing said one or more packets having an error by applying block erasure decoding to said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode said received packets.

7. The method of claim 6, wherein said block erasure decoder is a Bit Interleaved Parity (BIP-8) or byte-wise exclusive OR function.

8. The method of claim 6, further comprising the step of removing any padding at the end of said plurality of packets.

9. An error correction encoder, comprising:

a memory; and

at least one processor, coupled to the memory, operative to;

assemble M-T data packets;

append a sequence number and a payload integrity check to each of said M-T data packets; and

create T protection packets having said sequence number and payload integrity check, wherein a payload for each of said

10. The error correction encoder of claim 9, wherein said payload is equal to the check symbols of a block erasure code calculated over the corresponding symbols in said M-T packets.

11. The error correction encoder of claim 9, wherein said payload integrity check is a cyclic redundancy check.

12. The error correction encoder of claim 11, wherein said cyclic redundancy check is a CRC-32.

13. The error correction encoder of claim 9, wherein said payload integrity check employs an error correcting code.

14. An error correction decoder, comprising:

a memory; and

at least one processor, coupled to the memory, operative to;

receive a plurality of error-free packets and one or more packets having an error; and

reconstruct said one or more packets having an error by applying a block erasure decoder to a said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode said received packets.

15. The error correction decoder of claim 14, wherein said block erasure decoder is a bytewise exlusive OR or BIP-8.

16. The error correction decoder of claim 14, further comprising the step of removing any padding at the end of said M packets.

17. An error correction encoder for encoding message symbols, m₀ through m_N−

1, to generate a codeword that includes said message symbols, m₀ through m<sub>N−

1</sub>, and one or more check symbols, comprising;

a linear feedback shift register having one or more flip-flops to generate said check symbols after shifting said message symbols, m₀ through m<sub>N−

1</sub>, through said linear feedback shift register.

18. The error correction encoder of claim 17, wherein a payload containing said message symbols, m₀ through m_N−

1, comprises a symbol-wise exclusive or (XOR) of said message symbols, m₀ through M<sub>N−

1</sub>.

20. The error correction decoder of claim 17, wherein said error symbol is said remainder for T equal to one check symbol.

19. An error correction decoder for decoding a codeword that includes message symbols, m₀ through m_N−

1, and one or more check symbols, comprising;

a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting said message symbols, m₀ through m<sub>N−

1</sub>, and said one or more check symbols through said linear feedback shift register.

21. An error correction encoding method, comprising:

assembling a number of data packets;

appending a sequence number and a payload integrity check to each of said data packets; and

creating a number of protection packets having said sequence number and payload integrity check, wherein a payload for each of said protection packets are formed from corresponding symbols in said data packets.

22. The method of claim 21, wherein said payload of said protection packets is equal on a symbol-by-symbol basis to the check symbols of a block erasure code calculated over the corresponding symbols in said packets.

23. The method of claim 21, wherein said payload integrity check is a cyclic redundancy check.

24. The method of claim 23, wherein said cyclic redundancy check is a CRC-32.

25. The method of claim 21, wherein said payload integrity check employs an error correcting code.