Method and apparatus for delivering microcode updates through virtual machine operations

• US 20070074199A1
• Filed: 09/27/2005
• Published: 03/29/2007
• Est. Priority Date: 09/27/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Schoenberg, Sebastian
• Application Number:
  US11/237,034
• Publication Number:
  US 20070074199A1
• Time in Patent Office: Days
• US Class Current: 717/168
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors

Abstract

Instructions to change a microcode program of a virtual device are trapped and the replacement program is saved. Later, the microcode program is installed on one or more non-virtual devices. Software and systems using the method are also described.

Claims

1. A method comprising:

trapping an instruction to change a microcode update or microcode program of a virtual device;

saving a microcode update or microcode program associated with the trapped instruction; and

installing the microcode update or microcode program on one or more non-virtual computer devices.

2. The method of claim 1 wherein the virtual device is a virtual computer processor and the one or more non-virtual computer devices are non-virtual computer processors.

3. The method of claim 2 further comprising:

emulating a plurality of machine instructions of the virtual computer processor.

4. The method of claim 3 wherein emulating a plurality of machine instructions comprises:

executing a first group of the plurality of machine instructions directly on one of the one or more non-virtual processors; and

adjusting a state of the virtual processor in response to instructions of a second group of the plurality of machine instructions.

5. The method of claim 2 wherein the virtual computer processor implements at least one of an Intel®

IA-32 architecture or an Intel®

Itanium®

architecture.

6. The method of claim 2 wherein the one or more non-virtual computer processors implement at least one of an Intel®

IA-32 architecture or an Intel®

Itanium®

architecture.

7. The method of claim 1 wherein the virtual device is one of a network interface, a mass storage interface or a video interface.

8. The method of claim 1, wherein saving the microcode update or microcode program comprises storing it in a non-volatile memory.

9. The method of claim 1, wherein saving the microcode update or microcode program comprises writing it to a mass storage device.

10. The method of claim 1 further comprising:

analyzing the microcode update or microcode program to determine whether it is applicable to the one or more non-virtual devices.

11. A virtual machine manager comprising:

an emulator to emulate a plurality of machine instructions;

a detector to detect an attempt to update a microcode of a virtual device;

a storage to record a microcode update; and

an installer to install a recorded microcode update.

12. The virtual machine manager of claim 11 wherein the virtual device is a virtual processor.

13. The virtual machine manager of claim 12, wherein the emulator is to emulate a physical processor that implements at least one of an Intel®

IA-32 architecture or an Intel®

Itanium®

architecture.

14. The virtual machine manager of claim 11, wherein the installer is to install the recorded microcode update on at least one physical processor.

15. A system comprising:

at least one physical processor to emulate a machine containing at least one virtual processor and at least one virtual device and to trap a privileged instruction;

a memory; and

a non-volatile storage system to store a microcode update;

wherein

the privileged instruction is to update a microcode of one of the at least one virtual processor or the at least one virtual device.

16. The system of claim 15, further comprising:

at least one physical device; and

a microcode installer to install the microcode update on one of the at least one physical processor and the at least one physical device.

17. The system of claim 15 wherein a type of the at least one virtual processor is identical to a type of the plurality of physical processors.

18. The system of claim 15 wherein the at least one virtual processor implements at least one of an Intel®

IA-32 architecture or an Intel®

Itanium®

architecture.

19. The system of claim 15 wherein each of the plurality of physical processors implements at least one of an Intel®

IA-32 architecture or an Intel®

Itanium®

architecture.

20. The system of claim 15 wherein the privileged instruction to update the microcode is Write to Mode-Specific Register (“

WRMSR”

).

21. The system of claim 15 wherein the at least one virtual device is one of a network interface, a mass storage interface, or a video interface.

22. A machine-readable medium containing instructions that, when executed by a physical processor, cause the physical processor to perform operations comprising:

emulating a computer system containing a processor and at least one device;

trapping an instruction to update a microcode of the emulated processor or the at least one device;

storing an updated microcode to be installed by the instruction; and

installing the updated microcode.

23. The machine-readable medium of claim 22, containing additional instructions to cause the physical processor to perform operations comprising:

installing the updated microcode if the processor executes one of a reset sequence or a power-on sequence.

24. The machine-readable medium of claim 22, containing additional instructions to cause the physical processor to perform operations comprising:

monitoring a state of the physical processor; and

delaying the installing operation until the physical processor or device is in a predetermined state.

25. The machine-readable medium of claim 22 wherein the virtual processor implements at least one of an Intel®

IA-32 architecture or an Intel®

Itanium®

architecture.