Method for improving via's impedance

• US 20070074905A1
• Filed: 03/29/2006
• Published: 04/05/2007
• Est. Priority Date: 08/19/2005
• Status: Active Grant

• Current Assignee: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. (Hon Hai Precision Industry Co., Ltd.), Hon Hai Precision Industry Co., Ltd.
• Original Assignee: Hon Hai Precision Industry Co., Ltd.
• Inventors: Lin, Yu-Hsu, Li, Chuan-Bing, Yeh, Shang-Tsang
• Granted Patent: US 7,409,668 B2
• Time in Patent Office: Days
• US Class Current: 174/263
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H05K 1/0237 High frequency adaptations H05K1/0216 takes precedence
• CPC Class Codes: H05K 1/116 Lands, clearance holes or other lay-out details concerning the surrounding of a via
• CPC Class Codes: H05K 2201/09718 Clearance holes
• CPC Class Codes: H05K 2203/163 Monitoring a manufacturing process
• CPC Class Codes: H05K 3/0005 for designing circuits by computer
• CPC Class Codes: H05K 3/0047 Drilling of holes
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Abstract

A method is for controlling an impedance of a via of a printed circuit board. The Via is connected with a trace and includes a drill hole, a pad and an anti-pad. The method includes steps of: building a math model; testing whether an impedance of the via matching with an impedance of the trace; analyzing the impedance of the via if passing the testing; and adjusting parameters of the pad, the anti-pad, and the drill hole if fails testing, and returning to the simulating step, till impedance matching achieved. The method which can efficiently keep signals integrality and increase signal transmission speed.

Claims

1. A method of controlling an impedance of a via of a printed circuit board (PCB), the via is connected with traces and comprises a drill hole, a pad, and an anti-pad, the method comprising:

building a math model;

simulating a design of via and trace construction for the PCB by utilizing simulation software;

indicating whether an impedance of the via matches with an impedance of the trace in the simulation;

building the PCB according to the simulated design and verifying physical size of the via if impedance matching is achieved; and

adjusting parameters of the pad, the anti-pad, and the drill hole if impedance matching is not achieved, and returning to the simulating step, until impedance matching is achieved.

2. The method as claimed in claim 1, wherein the simulation software utilizes software of computer simulation technology (CST).

3. The method as claimed in claim 1, wherein the step of verifying comprising using time domain reflection (TDR).

4. The method as claimed in claim 1, wherein the step of adjusting parameters comprises one of methods of increasing a diameter of the anti-pad, decreasing a diameter of the pad, and decreasing a diameter of the drill hole.

5. A method of controlling an impedance of a via of a printed circuit board (PCB), the printed circuit board comprising signal layers, a ground layer, and a power layer, the method comprising:

defining a drill hole through the printed circuit board;

forming a pad encircling the drill hole and bonded with the signal layer;

forming an anti-pad encircling the drill hole;

building a math model;

simulating a design of a PCB with a via and traces with simulation software;

indicating whether an impedance of the via matches with an impedance of the traces in the simulated design;

building the PCB with the via using time domain reflection (TDR); and

adjusting parameters of the pad, the anti-pad, and the drill hole if impedance matching fails, and returning to the simulating step, until impedance matching is achieved.

6. The method as claimed in claim 5, wherein the simulation software utilizes software of computer simulation technology (CST).

7. The method as claimed in claim 5, wherein the step of adjusting parameters comprises one of methods of increasing a diameter of the anti-pad, decreasing a diameter of the pad, and decreasing a diameter of the drill hole.

8. A method of controlling an impedance of a via of a printed circuit board (PCB), the via is connected with traces and comprises a drill hole, a pad, and an anti-pad, an impedance of, the via is adjusted to match with an impedance of the traces, the method comprising:

building a math model;

simulating a design of a PCB with a via and traces with simulation software;

indicating whether an impedance of the via matches with an impedance of the traces in the simulated design;

building the PCB with the via using time domain reflection (TDR); and

adjusting diameters of the anti-pad, the pad, and the drill hole to reduce a stray capacitance and a parasitic inductance of the via, if impedance matching fails, and returning to the simulating step, until impedance matching is achieved.

9. The method as claimed in claim 8, wherein the simulation software utilizes software of computer simulation technology (CST).

10. The method as claimed in claim 8, wherein the step of adjusting comprises one of methods of increasing a diameter of the anti-pad, decreasing a diameter of the pad, and decreasing a diameter of the drill hole.