Strained silicon device

• US 20070075356A1
• Filed: 10/12/2006
• Published: 04/05/2007
• Est. Priority Date: 09/09/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Cheng-Chuan, Yang, Fu-Liang, Huang, Chien-Chao
• Granted Patent: US 8,569,845 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

Claims

1. A microelectronic device comprising:

a gate structure overlying a semiconductor substrate and for selectively operating a strained p-channel in the semiconductor substrate;

source and drain regions, each comprising;

a first doped region located adjacent to the channel and extending a first depth into the semiconductor substrate,

a second doped region located adjacent to the first doped region and extending a second depth into the semiconductor substrate greater than the first depth, and

a third doped region located adjacent to the second doped region and extending a third depth into the semiconductor substrate greater than the second depth.

2. The device of claim 1 wherein the source and drain regions are annealed following the formation of the third doped regions.

4. The device of claim 1 wherein the gate structure includes a silicide contact.

5. The device of claim 1 further comprising:

a clamping layer surrounding at least a portion of the gate structure.

6. The device of claim 1 wherein the first regions are lightly doped source/drain regions.

7. The device of claim 1 further comprising:

an L-shaped liner having a first portion abutting a sidewall of the gate structure and a second portion extending over the second doped region.

8. The device of claim 7 further comprising a relatively thin spacer extending over the first doped region.

9. The device of claim 8 wherein the relatively thin spacer has a width of about 350 Angstroms and wherein the second doped region has a width of 300 Angstroms extending from an outer edge of the relatively thin spacer.

3. The device of claim wherein the third doped region includes a SiGe doped portion.