Cobalt silicon contact barrier metal process for high density semiconductor power devices

• US 20070075360A1
• Filed: 09/30/2005
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Abandoned Application

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Ng, Daniel, Tai, Sung-Shan, Li, Tiesheng, Chang, Hong
• Application Number:
  US11/240,255
• Publication Number:
  US 20070075360A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a source contact opening opened on top of an area extended over the body region and the source region through a protective insulation layer wherein the area further has a cobalt-silicide layer disposed near a top surface of the substrate. The MOSFET cell further includes a Ti/TiN conductive layer covering the area interfacing with the cobalt-silicide layer over the source contact opening. The MOSFET cell further includes a source contact metal layer formed on top of the Ti/TiN conductive layer ready to form source-bonding wires thereon.

Claims

1. A trenched metal oxide semiconductor field effect transistor (MOSFET) cell comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein said MOSFET cell further comprising:

a source contact opening opened on top of an area extended over said body region and said source region through a protective insulation layer wherein said area further comprising a cobalt-silicide layer disposed near a top surface of said substrate.

2. The MOSFET cell of claim 1 further comprising:

a Ti/TiN conductive layer covering said area with said cobalt-silicide layer over said source contact opening.

3. The MOSFET cell of claim 2 further comprising:

a source contact metal layer formed on top of said Ti/TiN conductive layer ready to form source bonding wires thereon.

4. The MOSFET cell of claim 1 further comprising:

a gate contact opening opened on top of said trenched gate through said protective insulation layer.

5. The MOSFET cell of claim 4 further comprising:

a Ti/TiN conductive layer covering said gate opening in electrical contact with said trenched gate.

6. The MOSFET cell of claim 5 further comprising:

a gate contact metal layer formed on top of said Ti/TiN conductive layer ready to form a gate bonding wire thereon.

7. A method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) cell comprising processing steps to form a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein method further comprising:

opening a source contact opening on top of an area extended over said body region and said source region through a protective insulation layer and forming a cobalt-silicide layer on said area near a top surface of said substrate.

8. The method of claim 7 further comprising:

forming a Ti/TiN conductive layer for covering said cobalt-silicide layer and over said source contact opening.

9. The method of claim 8 further comprising:

forming contact metal layer on top of said Ti/TiN conductive layer and patterning said contact metal layer into a source metal contact ready to form source bonding wires thereon.

10. The method of claim 7 further comprising:

opening a gate contact opening on top of said trenched gate through said protective insulation layer.

11. The method of claim 10 further comprising:

forming a Ti/TiN conductive layer for covering said gate opening in electrical contact with said trenched gate.

12. The MOSFET cell of claim 11 further comprising:

forming a contact metal layer on top of said Ti/TiN conductive layer and patterning said contact metal layer into a gate metal contact ready to form a gate bonding wire thereon.

13. The method of claim 7 wherein:

said step of forming a cobalt-silicide layer on said area near a top surface of said substrate includes a step of sputtering cobalt ions on said area.

14. The method of claim 13 wherein:

said step of sputtering cobalt ions on said area further comprising sputtering said cobalt ions to a depth of approximately 100 to 300 Angstroms into said substrate.

15. The method of claim 13 wherein:

said step of forming a cobalt-silicide layer on said area near a top surface of said substrate further includes a step of carrying out a cobalt-silicide RTA following said step of sputtering cobalt ions on said area.

16. The method of claim 13 wherein:

said step of forming a cobalt-silicide layer on said area near a top surface of said substrate further includes a step of carrying out a first cobalt-silicide RTA at a temperature substantially higher than 475 degree Celsius following said step of sputtering cobalt ions on said area.

17. The method of claim 16 wherein:

said step of forming a cobalt-silicide layer on said area near a top surface of said substrate further includes a step of carrying out a cobalt wet etch following said first cobalt-silicide RTA.

18. The method of claim 17 wherein:

said step of forming a cobalt-silicide layer on said area near a top surface of said substrate further includes a step of carrying out a second cobalt-silicide RTA at a temperature approximately 450 to 800 degrees Celsius following said cobalt wet etch.

19. The method of claim 18 wherein:

said step of forming a cobalt-silicide layer on said area near a top surface of said substrate further includes a step of carrying out a third cobalt-silicide RTA following said second cobalt-silicide RTA.

20. The method of claim 13 further comprising:

sputtering a Ti/TiN conductive layer on top of said MOSFET device covering said cobalt-silicide area and said source contact opening.

21. The method of claim 20 further comprising:

sputtering a metal layer composed of AlSiCu or AlCu on top of said Ti/TiN layer and patterning said metal layer into a source contact metal layer.