Semiconductor chip and semiconductor device

• US 20070075424A1
• Filed: 09/22/2006
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakanishi, Hiroyuki, Mori, Haruya
• Granted Patent: US 7,538,442 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

In the peripheral part of a semiconductor chip, third electrode pads for wire bonding and plate wiring and first electrode pads dedicated to wire bonding are provided. On the other hand, second electrode pads dedicated to plate wiring are provided on an inner part away from the edge of the semiconductor chip. Further, the first and second electrode pads are connected via metal bypass layers, respectively. In the case of wire bonding, the first and third electrode pads are used and the third electrode pads are encapsulated with an insulating layer. Further, in the case of plate wiring, the second and third electrode pads are used and the first electrode pads are covered with an insulating layer. This realizes a semiconductor chip which has great versatility and which can be used in semiconductor packages of various types.

Claims

1. A semiconductor chip, comprising:

a semiconductor element; and

a plurality of electrode sections, to or from each of which a signal is inputted or outputted from or to the semiconductor element, respectively,

the semiconductor element and the electrode sections being provided on a main surface of the semiconductor chip,

the electrode sections including;

at least one first electrode section disposed in a peripheral part of the main surface; and

at least one second electrode section disposed on an inner part of the first electrode section of the main surface, and

the first and second electrode sections being electrically connected.

2. A semiconductor device, comprising a semiconductor chip,

said semiconductor chip, including:

a semiconductor element; and

a plurality of electrode sections, to or from each of which a signal is inputted or outputted from or to the semiconductor element, respectively,

the semiconductor element and the electrode sections being provided on a main surface of the semiconductor chip,

the electrode sections including;

at least one first electrode section disposed in a peripheral part of the main surface; and

at least one second electrode section disposed on an inner part of the first electrode section of the main surface,

the first and second electrode sections being electrically connected,

the main surface of the semiconductor chip having thereon a plurality of external connection terminals via which the electrode sections are connected to an external device, and

at least one of the external connection terminals being connected to said at least one second electrode section.

3. The semiconductor device according to claim 2, wherein said at least one first electrode section is covered with an insulating layer.

4. The semiconductor device according to claim 3, wherein said at least one external connection terminals is disposed in a region which overlaps said at least one first electrode section, when viewed from a direction normal to the main surface of the semiconductor chip.

5. A semiconductor device, comprising a semiconductor chip,

said semiconductor chip, including:

a semiconductor element; and

a plurality of electrode sections, to or from each of which a signal is inputted or outputted from or to the semiconductor element, respectively,

the semiconductor element and the electrode sections being provided on a main surface of the semiconductor chip,

the electrode sections including;

at least one first electrode section disposed in a peripheral part of the main surface; and

at least one second electrode section disposed on an inner part of the first electrode section of the main surface,

the first and second electrode sections being electrically connected,

said semiconductor device, further comprising a stacked substrate on which the semiconductor chip is stacked,

the stacked substrate including;

a plurality of external connection terminals; and

a plurality of conductive sections being connected to the external connecting terminals, respectively, and

at least one of the conductive sections being connected to said at least one first electrode section via at least one wire.

6. The semiconductor device according to claim 5, wherein:

the semiconductor chip is fixed to one surface of the stacked substrate,

at least one of the external connection terminals is disposed in a region of another surface of the stacked substrate, the region overlapping the semiconductor chip when viewed from a direction normal to the surface of the substrate, and

said at least one of the conductive sections, connected to said at least one external connection terminals disposed in the region, connects said at least one external connection terminals and said at least one wire via one of through holes provided in the stacked substrate.

7. The semiconductor device according to claim 5, wherein

the semiconductor chip, said at least one wire, and said at least one conductive section are sealed with an insulating material.