Inspection device and inspection method for active matrix panel, and manufacturing method for active matrix organic light emitting diode panel

• US 20070075727A1
• Filed: 09/05/2006
• Published: 04/05/2007
• Est. Priority Date: 05/21/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nakano, Daiju, Sakaguchi, Yoshitami
• Granted Patent: US 7,317,326 B2
• Time in Patent Office: Days
• US Class Current: 324/762.90
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2330/10 Dealing with defective pixels
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3225 using an active matrix

Abstract

An inspection method includes an array process of forming a TFT array on a substrate to fabricate an active matrix panel, an inspection process of carrying out a performance test on the fabricated active matrix panel, and a cell process of mounting an OLED on the active matrix panel after the inspection process. In the inspection process, variation in parasitic capacitance through a pixel electrode is measured when driving TFTs constituting the active matrix fabricated in the array process are turned on and when the driving TFTs are turned off, and open/short defects in the driving TFTs are thereby inspected.

Claims

1-9. -9. (canceled)

10. An inspection method for an active matrix panel for inspecting an active matrix panel prior to formation of an organic light emitting diode, comprising the steps of:

measuring a value based on parasitic capacitance through a pixel electrode in an off state of a driving thin film transistor constituting the active matrix panel;

measuring a value based on the parasitic capacitance through the pixel electrode in an on state of the driving thin film transistor; and

inspecting any of open and short defects of the driving thin film transistor based on a measured off state value and a measured on state value.

11. The inspection method for an active matrix panel according to claim 10, wherein each of the values based on the parasitic capacitance through the pixel electrode represents a transient current which flows from the pixel electrode side to a source side through the parasitic capacitance.

12. The inspection method for an active matrix panel according to claim 10, further comprising the step of:

estimating the off state value based on the parasitic capacitance on each line of inspection wiring constituting the active matrix panel while setting the driving thin film transistors of all pixels subjected to alternating-current coupling directly with the inspection wiring simultaneously to the off state.

13. The inspection method for an active matrix panel according to claim 10, further comprising the step of:

estimating the on state value based on the parasitic capacitance on each line of inspection wiring constituting the active matrix panel while setting the driving thin film transistors of all pixels subjected to alternating-current coupling directly with the inspection wiring simultaneously to the on state.

20. The inspection method for an active matrix panel according to claim 10,

wherein each of the values based on the parasitic capacitance through the pixel electrode represents a transient current which flows from the pixel electrode side to a source side through the parasitic capacitance.

further comprising the step of estimating the off state value based on the parasitic capacitance on each line of inspection wiring constituting the active matrix panel while setting the driving thin film transistors of all pixels subjected to alternating-current coupling directly with th inspection wiring simultaneously to the off state.

further comprising the step of:

estimating the on state value based on the parasitic capacitance on each line of inspection wiring constituting the active matrix panel while setting the driving thin film transistors of all pixels subjected to alternating-current coupling directly with the inspection wiring simultaneously to the on state.

14. A manufacturing method for an active matrix organic light emitting diode panel, comprising the steps of:

forming a thin film transistor array on a substrate and thereby fabricating an active matrix panel;

inspecting a function of the fabricated active matrix panel; and

mounting an organic light emitting diode on the active matrix panel after the inspection process, wherein the inspecting step further comprises the step of;

measuring variations in parasitic capacitance through a pixel electrode when a driving thin film transistor constituting the active matrix panel fabricated in the array process is turned on and off, and thereby to inspect any of open and short defects of the driving thin film transistor.

15. The manufacturing method for an active matrix organic light emitting diode panel according to claim 14, wherein the inspecting step further comprises the step of:

measuring the variation in parasitic capacitance of pixels constituting the active matrix panel and thereby to find the number of pixels having open and short defects in the driving thin film transistors thereof.

16. The manufacturing method for an active matrix organic light emitting diode panel according to claim 14, wherein the inspecting step further comprises the step of:

estimating unevenness caused upon formation of pixel circuits constituting the active matrix panel from unevenness of the variation in parasitic capacitance of pixels constituting the active matrix panel.

17. The manufacturing method for an active matrix organic light emitting diode panel according to claim 14, wherein the inspecting step further comprises the steps of:

estimating the parasitic capacitance on each line of inspection wiring constituting the active matrix panel while setting the driving thin film transistor of a pixel subjected to alternating-current coupling directly with a corresponding line of the inspection wiring to an on state; and

estimating the number of pixels having open defects in the driving thin film transistors thereof by use of a difference between a maximum value of the estimated parasitic capacitance and individual parasitic capacitance.

18. The manufacturing method for an active matrix organic light emitting diode panel according to claim 14, wherein the inspecting step further comprises the steps of:

estimating the parasitic capacitance on each line of inspection wiring constituting the active matrix panel while setting the driving thin film transistor of a pixel subjected to alternating-current coupling directly with a corresponding line of the inspection wiring to an off state; and

estimating the number of pixels having short defects in the driving thin film transistors thereof by use of a difference between a minimum value of the estimated parasitic capacitance and individual parasitic capacitance.

19. The manufacturing method for an active matrix organic light emitting diode panel according to claim 14, wherein the inspecting step further comprises the step of:

estimating the parasitic capacitance on each line of inspection wiring when the driving thin film transistors of pixels subjected to alternating-current coupling directly with the inspection wiring are turned on an off; and

estimating the number of open and short defects on each line of the inspection wiring by use of a difference among a minimum value and a maximum value of the estimated parasitic capacitance and the parasitic capacitance on each line of the inspection wiring.

21. The manufacturing method for an active matrix organic light emitting diode panel according to claim 14,

wherein the inspecting step further comprises the step of:

measuring the variation in parasitic capacitance of pixels constituting the active matrix panel and thereby to find the number of pixels having open and short defects in the driving thin film transistors thereof;

wherein the inspecting step further comprises the step of;

estimating unevenness;

caused upon formation of pixel circuits constituting the active matrix panel from unevenness of the variation in parasitic capacitance of pixels constituting the active matrix panel; and

wherein the inspecting step further comprises the steps of;

estimating the parasitic capacitance on each line of inspection wiring constituting the active matrix panel while setting the driving thin film transistor of a pixel subjected to e-current coupling directly with a corresponding line of the inspection wiring to an on state; and

estimating the number of pixels having open defects in the driving thin film transistors thereof by use one of;

a difference between a maximum value of the estimated parasitic capacitance and individual parasitic capacitance, and

a difference between a minimum value of the estimated parasitic capacitance and individual parasitic capacitance.

22. The manufacturing method for an active matrix organic light emitting diode panel according to claim 14,

wherein the inspecting step further comprises the step of:

measuring the variation in parasitic capacitance of pixels constituting the active matrix panel and thereby to find the number of pixels having open and short defects in the driving thin film transistors thereof.;

wherein the inspecting step further comprises the step of;

estimating unevenness caused upon formation of pixel circuits constituting the active matrix panel from unevenness of the variation in parasitic capacitance of pixels constituting the active matrix panel; and

wherein the inspecting step further comprises the step of;

estimating the parasitic capacitance on each line of inspection wiring when the driving thin film transistors of pixels subjected to alternating-current coupling directly with the inspection wiring are turned on and off; and

estimating the number of open and short defects on each line of the inspection wiring by use of a difference among a minimum value and a maximum value of the estimated parasitic capacitance and the parasitic capacitance on each line of the inspection wiring.