Reconfigurable network on a chip

• US 20070075734A1
• Filed: 10/03/2005
• Published: 04/05/2007
• Est. Priority Date: 10/03/2005
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Ramos, Jeremy, Stackelhouse, Scott, Troxel, Ian
• Granted Patent: US 7,382,154 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

An architecture for a reconfigurable network that can be implemented on a semiconductor chip is disclosed, which includes a hierarchical organization of network components and functions that are readily programmable and highly flexible. Essentially, a reconfigurable network on a chip is disclosed, which includes aspects of reconfigurable computing, system on a chip, and network on a chip designs. More precisely, a reconfigurable network on a chip includes a general purpose microprocessor for implementing software tasks, a plurality of on-chip memories for facilitating the processing of large data structures as well as processor collaboration, a plurality of reconfigurable execution units including self-contained, individually reconfigurable programmable logic arrays, a plurality of configurable system interface units that provide interconnections between on-chip memories, networks or buses, an on-chip network including a network interconnection interface that enables communication between all reconfigurable execution units, configurable system interface units and general purpose microprocessors, a fine grain interconnect unit that gathers associated input/output signals for a particular interface and attaches them to a designated system interface resource, and a plurality of input/output blocks that supply the link between an on-chip interface resource and a particular external network or device interface. Advantageously, the network minimizes the configuration latency of the reconfigurable execution units and also enables reconfiguration on-the-fly.

Claims

1. A reconfigurable network, comprising:

at least one memory unit;

at least one processing unit coupled to said at least one memory unit;

at least one reconfigurable execution unit coupled to said at least one processing unit;

a network interface unit coupled to said at least one reconfigurable execution unit;

at least one configurable system interface unit coupled to said network interface unit; and

a fine grain interconnect unit coupled to said at least one configurable system interface unit.

2. The reconfigurable network of claim 1, further comprising:

at least one input/output unit coupled to said fine grain interconnect unit.

3. The reconfigurable network of claim 1, wherein the reconfigurable network is disposed on a semiconductor chip.

4. The reconfigurable network of claim 1, wherein said at least one memory unit comprises a volatile memory device, said at least one processing unit comprises four microprocessors, said at least one reconfigurable execution unit comprises twelve reconfigurable execution units, and said at least one configurable system interface unit comprises twelve configurable system interface units.

5. The reconfigurable network of claim 1, wherein said at least one processing unit comprises an embedded microprocessor.

6. The reconfigurable network of claim 1, wherein said network interface unit comprises an on-chip network operable to interconnect said at least one reconfigurable interface unit, said at least one configurable system interface unit, and said at least one processing unit for data communications therebetween.

7. The reconfigurable network of claim 1, wherein said at least one reconfigurable execution unit comprises at least one programmable logic array.

8. The reconfigurable network of claim 1, wherein said at least one configurable system interface unit comprises a configurable data communications interface operable to interconnect at least two of a memory unit, a network and a bus for data communications therebetween.

9. The reconfigurable network of claim 1, wherein said fine grain interconnect unit comprises at least one programmable routing device.

10. The reconfigurable network of claim 1, further comprising:

at least one input/output unit coupled to said fine grain interconnect unit, wherein said at least one input/output unit comprises at least one input/output pad, at least one register, and at least one tri-state buffer.

11. A reconfigurable network on a chip, comprising:

means for storing data;

means for processing said data, coupled to said means for storing data;

reconfigurable execution means for executing a plurality of configuration instructions, coupled to said means for storing data;

network interface means for interconnecting said means for processing and said reconfigurable execution means; and

configurable system interface means for interconnecting said network interface means with a fine grain interconnect means, said fine grain interconnect means for receiving a plurality of associated input/output signals and attaching said plurality of associated input/output signals to said configurable system interface means.

12. A method for increasing the configuration adaptability and processing speed of a network on a chip, comprising the steps of:

coupling at least one memory unit to at least one processing unit on the chip;

coupling at least one reconfigurable execution unit on the chip to said at least one processing unit;

coupling a network interface unit on the chip to said at least one reconfigurable execution unit;

coupling at least one configurable system interface unit on the chip to said network interface unit; and

coupling a fine grain interconnect unit on the chip to said at least one configurable system interface unit.

13. The method of claim 12, further comprising the step of:

coupling at least one input/output unit on the chip to said fine grain interconnect unit.

14. The method of claim 12, wherein the chip is a CMOS chip.

15. The method of claim 12, wherein the chip is an SOI chip.

16. The method of claim 12, wherein said at least one memory unit comprises a volatile memory device, said at least one processing unit comprises four microprocessors, said at least one reconfigurable execution unit comprises twelve reconfigurable execution units, and said at least one configurable system interface unit comprises twelve configurable system interface units.

17. The method of claim 12, wherein said at least one processing unit comprises an embedded microprocessor.

18. The method of claim 12, wherein the coupling steps further comprise interconnecting said at least one reconfigurable interface unit, said at least one configurable system interface unit, and said at least one processing unit for data communications therebetween.

19. The method of claim 12, wherein said at least one reconfigurable execution unit comprises at least one programmable logic array.

20. The method of claim 12, wherein said fine grain interconnect unit comprises at least one programmable routing device.