Radio frequency power amplifier

• US 20070075784A1
• Filed: 07/31/2006
• Published: 04/05/2007
• Est. Priority Date: 02/05/2004
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Pettersson, Ola, Litwin, Andrej
• Application Number:
  US11/496,133
• Publication Number:
  US 20070075784A1
• Time in Patent Office: Days
• US Class Current: 330/311
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2203/45464 the CSC comprising one or more coils
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages

Abstract

The present invention relates to a cascode radio frequency power amplifier, including at least two cascaded MOS transistors formed in a mutual substrate, where the bulk nodes of the transistors are isolated from each other and connected to the respective source of each transistor. The present invention also teaches that the drain of the topmost transistor is connected to the power supply through an inductive load, and that the gate of each upper transistor is equipped with a self-biasing circuit connected at least between the drain and the gate of the respective upper transistor.

Claims

1. A cascode radio frequency power amplifier, comprising:

at least two cascaded MOS transistors formed in a mutual substrate, each comprising bulk nodes, and extending between a topmost transistor and a bottom transistor, and wherein the MOS transistors not including the bottom transistor comprise upper transistors,

wherein the bulk nodes of the transistors are electrically isolated from each other and connected to a respective source of each transistor,

wherein a drain of the topmost transistor is connected to a power supply potential through an inductive load, and

wherein a gate of one or more upper transistors is coupled to a self-biasing circuit connected at least between the drain and the gate of the respective upper transistor.

2. The amplifier of claim 1, wherein each of the upper transistors are coupled to a respective self-biasing circuit.

3. The amplifier of claim 1, wherein the bulk nodes of at least the upper transistors are each isolated from the substrate.

4. The amplifier of claim 1, wherein the transistors comprise triple well CMOS transistors, wherein a well of each respective transistor is isolated from the bulk, and wherein the well of each respective transistor is short circuited to the source thereof.

5. The amplifier of claim 1, wherein the transistors comprise CMOS transistors on a Silicon-on-Insulator substrate, wherein a well of each respective transistor is isolated from a bulk portion of the substrate, and wherein the well of each respective transistor is short circuited to its respective source.

6. The amplifier of claim 1, wherein the transistors and the self-biasing circuits are configured to bias the transistors to force such transistors into predetermined operating regions thereof, thereby maximizing the amplifier gain.

7. The amplifier of claim 1, wherein transistors and the self-biasing circuits are configured to bias the transistors into a linear operating region thereof, thereby optimizing the amplifier linearity.

8. A radio frequency amplifier, comprising:

at least two series connected MOS transistors formed in a mutual substrate and each comprising a bulk node, wherein one of the transistors comprises a topmost transistor and has a terminal coupled to a supply potential through a load, and wherein one of the transistors comprises a bottom transistor and has a terminal coupled to a reference potential, and a control terminal forming an amplifier input,

wherein the bulk nodes of each transistor is coupled to a respective source terminal thereof, and wherein the bulk nodes of at least two of the MOS transistors are electrically isolated from one another.

9. The amplifier of claim 8, further comprising a self-biasing circuit coupled between a drain terminal and a control terminal of at least one of the transistors that is not the bottom transistor.

10. The amplifier of claim 9, wherein each of the transistors, excluding the bottom transistor, has a self-biasing circuit associated therewith coupled between the control terminal and the drain terminal thereof.

11. The amplifier of claim 9, wherein the self-biasing circuit is configured to bias the at least one transistor in a linear operating range thereof.

12. The amplifier of claim 8, wherein the bulk nodes of each of the transistors are electrically isolated from one another.

13. The amplifier of claim 8, wherein the bulk node is coupled to a respective source terminal of each of the transistors.