PHASE LOCKED LOOP AND METHOD FOR ADJUSTING THE FREQUENCY AND PHASE IN THE PHASE LOCKED LOOP

• US 20070075785A1
• Filed: 08/31/2006
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Schmatz, Martin, Wehrli, Silvan, Morf, Thomas, Kossel, Marcel
• Granted Patent: US 7,403,073 B2
• Time in Patent Office: Days
• US Class Current: 331/16
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.

Claims

1. Phase locked loop comprising:

a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and of generating a digital value representing the phase difference between the reference signal and the oscillator signal;

a state machine for phase acquisition capable of generating a control value depending on the digital value; and

a controllable oscillator capable of generating the oscillator signal depending on the control value.

2. A phase locked loop according to claim 1,

wherein the time to digital converter comprises a delay line with several delay elements that can be sampled by a sampling clock;

and

wherein the sampling clock is gained from a conjunction of the outputs of the phase frequency detector.

3. A phase locked loop according to claim 2,

wherein an additional delay line is arranged in parallel to the delay line;

and

wherein the delay elements of the additional delay line have other delays than the delay elements of the delay line.

4. A phase locked loop according to claim 1, wherein the state machine for phase acquisition performs steps comprising:

at a determined point of time the change between the digital value and a previous digital value is calculated;

the change is mapped by means of a look up table to a corresponding correction step size; and

the control value is updated taking the correction step size into account.

5. A phase locked loop according to claim 1 wherein a further state machine is provided for performing a frequency acquisition.

6. A phase locked loop according to claim 5, wherein it is switched from the phase acquisition to the frequency acquisition, when the phase difference exceeds a determined value.

7. A phase locked loop according to claim 5, wherein the phase acquisition is activated when the oscillator frequency is equal to the reference frequency.

8. A phase locked loop according to claim 1, wherein the state machine for frequency acquisition performs the steps comprising:

if at a determined point of time a direction signal, indicating whether the oscillator signal leads or lags the reference signal, is still unchanged, the control value is updated taking a correction step size into account; and

if at the determined point of time the direction signal has changed, a new correction step size is calculated, and the control value is updated taking the new correction step size into account.

9. A phase locked loop according to claim 8, wherein for updating the control value the new correction step size and an average value which is calculated by means of previous control values is taken into account.

10. A phase locked loop according to claim 8, wherein a flip-flop is coupled to the phase frequency detector for generating the direction signal.

11. A clock and data recovery circuit comprising:

a phase locked loop comprising;

a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and of generating a digital value representing the phase difference between the reference signal and the oscillator signal;

a state machine for phase acquisition capable of generating a control value depending on the digital value; and

a controllable oscillator capable of generating the oscillator signal depending on the control value; and

sampling latches capable of sampling input data and being triggered by the phase locked loop.

12. A method for monitoring the jitter in a phase locked loop, the method comprising:

comparing a reference signal with an oscillator signal;

generating a digital value representing the phase difference between the reference signal and the oscillator signal;

generating a control value depending on the digital value; and

generating the oscillator signal depending on the control value; and

wherein the deviation between the sampled digital value and a desired digital value is calculated, which represents the amount of jitter.

13. A method for adjusting the phase in a phase locked loop, the method comprising:

determining, at a determined point of time, a digital value representing the phase difference between a reference signal and an oscillator signal;

calculating the change between the digital value and a previous digital value;

calculating a control value taking the change between the digital value and a previous digital value into account; and

wherein the oscillator signal is adapted to the control value.

14. A method for adjusting the frequency in a phase locked loop, the method comprising:

comparing, at a determined point of time, a reference signal and an oscillator signal;

determining a direction signal indicating whether the oscillator signal leads or lags the reference signal;

if at the determined point of time the direction signal is unchanged, updating a control value for controlling an oscillator of the phase locked loop is updated, the updated control value taking a correction step size into account; and

if at the determined point of time the direction signal has changed;

calculating a new correction step size; and

updating the control value, the updated control value taking the new correction step size into account.