Daisy chain cascading devices

• US 20070076502A1
• Filed: 07/31/2006
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Abandoned Application

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki, Pyeon, Hong
• Application Number:
  US11/496,278
• Publication Number:
  US 20070076502A1
• Time in Patent Office: Days
• US Class Current: 365/221
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: G06F 13/4256 using a clocked protocol
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data, address and command information, and control signals to the second device from the first device. The devices coupled in the daisy chain comprise a serial input (SI) and a serial output (SO). Information is input to a device via the SI. The information is output from the device via the SO. The SO of an earlier device in the daisy chain cascade is coupled to the SI of a device later in the daisy chain cascade. Information input to the earlier device via the device'"'"'s SI is passed through the device and output from the device via the device'"'"'s SO. The information is then transferred to the later device'"'"'s SI via the connection from the earlier device'"'"'s SO and the later device'"'"'s SI.

Claims

1. An apparatus having a plurality of devices configured in a daisy chain cascade arrangement, the apparatus comprising:

a first memory device having;

(a) memory,

(b) a first input for receiving address information associated with a memory location in the memory,

(c) a first output configured to output data contained in the memory location from the first device; and

a second memory device having;

(a) a first input coupled to the first output of the first device and configured to receive the data outputted from the first device.

2. An apparatus as defined in claim 1 wherein the data is serially transferred from the first output of the first memory device to the first input of the second memory device.

3. An apparatus as defined in claim 1 wherein the first memory device further has:

(a) a second input for receiving an enable signal that is used to enable the first input of the first memory device to receive the address information, and

(b) a second output for outputting the enable signal.

4. An apparatus as defined in claim 3 wherein the second memory device has a second input coupled to the second output of the first memory device for receiving the enable signal at the second memory device.

5. An apparatus as defined in claim 1 wherein the first memory device has:

a second input for receiving an enable signal that is used to enable the data to be output on the first output of the first memory device; and

a second output for outputting the enable signal from the first memory device.

6. An apparatus as defined in claim 5 wherein the second memory device has a second input that is coupled to the second output of the first memory device for receiving the enable signal at the second memory device.

7. An apparatus as defined in claim 1 wherein the first memory device and second memory device each have a second input for receiving a clock signal that is used by the first and second memory devices to accommodate the transfer of the accessed data from the first output of the first memory device to the first input of the second memory device.

8. An apparatus as defined in claim 7 wherein the first memory device has a second output coupled to the second input of the second memory device for transferring the clock signal from the first memory device to the second memory device.

9. A method comprising:

inputting, into a first input of a first memory device, address information associated with a memory location of memory contained in the first memory device;

accessing data in memory contained in the first memory device at the memory location; and

coupling a first output of the first device to a first input of a second memory device to allow the accessed data to be transferred from the first memory device to the second memory device.

10. A method as defined in claim. 9 further comprising:

coupling a clock signal to the first memory device and the second memory device, the clock signal being used by the first memory device and second memory device to accommodate the transfer of the accessed data from the first memory device to the second memory device.

11. A method as defined in claim 10 wherein the clock signal is coupled to a second input of the second memory device from a second output of the first memory device.

12. A method as defined in claim 9 further comprising:

inputting into a second input of the first memory device an enable signal that is used to enable the address information to be input to the first input of the first memory device;

outputting the enable signal from a second output of the first memory device; and

coupling the second output of the first memory device to a second input of the second memory device to allow the enable signal to be transferred from the first memory device to the second memory device.

13. A method as defined in claim 9 further comprising:

inputting, into a second input of the first memory device, an enable signal that is used to enable the accessed data to be output from the first memory device;

outputting the enable signal from a second output of the first memory device; and

coupling the second output of the first memory device to a second input of the second memory device to allow the enable signal to be transferred from the first memory device to the second memory device.

14. A method as defined in claim 9 wherein the accessed data is serially transferred from the first output of the first memory device to the first input of the second memory device.

15. An apparatus comprising:

means for inputting, into a first input of a first memory device, address information associated with a memory location of memory contained in the first memory device;

means for accessing data in memory contained in the first memory device at the memory location; and

means for coupling a first output of the first device to a first input of a second memory device to allow the accessed data to be transferred from the first memory device to the second memory device.

16. An apparatus as defined in claim 15 further comprising:

means for coupling a clock signal to the first memory device and the second memory device, the clock signal being used by the first memory device and second memory device to accommodate the transfer of the accessed data from the first memory device to the second memory device.

17. An apparatus as defined in claim 16 wherein the clock signal is coupled to a second input of the second memory device from a second output of the first memory device.

18. An apparatus as defined in claim 15 further comprising:

means for inputting into a second input of the first memory device an enable signal that is used to enable the address information to be input to the first input of the first memory device;

means for outputting the enable signal from a second output of the first memory device; and

means for coupling the second output of the first memory device to a second input of the second memory device to allow the enable signal to be transferred from the first memory device to the second memory device.

19. An apparatus as defined in claim 15 further comprising:

means for inputting, into a second input of the first memory device, an enable signal that is used to enable the accessed data to be output from the first memory device;

means for outputting the enable signal from a second output of the first memory device; and

means for coupling the second output of the first memory device to a second input of the second memory device to allow the enable signal to be transferred from the first memory device to the second memory device.

20. An apparatus as defined in claim 15 wherein the accessed data is serially transferred from the first output of the first memory device to the first input of the second memory device.