Three-Dimensional Mask-Programmable Read-Only Memory

• US 20070076509A1
• Filed: 09/07/2006
• Published: 04/05/2007
• Est. Priority Date: 08/28/2002
• Status: Abandoned Application

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Application Number:
  US11/309,657
• Publication Number:
  US 20070076509A1
• Time in Patent Office: Days
• US Class Current: 365/230.30
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

The present invention discloses several improved three-dimensional mask-programmable read-only memories (3D-MPROM), including interleaved self-aligned pillar-shaped 3D-MPROM (ISP 3D-MPROM), separate self-aligned pillar-shaped 3D-MPROM (SSP 3D-MPROM), interleaved self-aligned natural-junction 3D-MPROM (ISN 3D-MPROM) and separate self-aligned natural-junction 3D-MPROM (SSN 3D-MPROM). They have larger memory capacity and lower manufacturing cost.

Claims

1. A three-dimensional mask-programmable read-only memory (3D-MPROM), including a plurality of vertically stacked memory levels, comprising:

a first address-selection line;

a config-dielectric located above said first address-selection line and comprising at least an info-opening;

a second address-selection line located above said config-dielectric;

a 3D-MPROM layer between said first and second address-selection lines and having a rectangular footprint;

wherein one pair of opposing edges of said 3D-MPROM layer are aligned with two edges of said first address-selection line, and the other pair of opposing edges of said 3D-MPROM layer are aligned with two edges of said second address-selection line.

2. The 3D-MPROM according to claim 1, wherein the dimension of said 3D-MPROM layer along the direction of said second address-selection line is equal to the width of said first address-selection line.

3. The 3D-MPROM according to claim 1, wherein the dimension of said 3D-MPROM layer along the direction of said first address-selection line is equal to the width of said second address-selection line.

4. The 3D-MPROM according to claim 1, wherein the dimension of said info-opening along the direction of said second address-selection line is larger than the width of said first address-selection line.

5. The 3D-MPROM according to claim 1, wherein the dimension of said info-opening along the direction of said first address-selection line is larger than the width of said second address-selection line.

6. The 3D-MPROM according to claim 1, wherein said first or second address-selection line comprises semiconductor material.

7. The 3D-MPROM according to claim 1, wherein said first or second address-selection line comprises metallic material.

8. A three-dimensional mask-programmable read-only memory (3D-MPROM), including a plurality of vertically stacked memory levels, comprising:

a first address-selection line;

a config-dielectric located above said first address-selection line and comprising at least an info-opening;

a second address-selection line located above said config-dielectric;

wherein a natural junction is formed at the intersection between said first and second address-selection lines, said natural junction having a lower resistance when the current flows in one direction than when the current flows in the opposite direction.

9. The 3D-MPROM according to claim 8, wherein said natural junction is a p-n junction.

10. The 3D-MPROM according to claim 9, wherein the topmost portion of said first address-selection comprises a doped semiconductor material, and the lowermost portion of said second address-selection comprises an oppositely doped semiconductor material.

11. The 3D-MPROM according to claim 8, wherein said natural junction is a Schottky junction.

12. The 3D-MPROM according to claim 11, wherein the topmost portion of said first address-selection comprises a metallic material, and the lowermost portion of said second address-selection comprises a doped semiconductor material.

13. The 3D-MPROM according to claim 11, wherein the topmost portion of said first address-selection comprises a doped semiconductor material, and the lowermost portion of said second address-selection comprises a metallic material.

14. The 3D-MPROM according to claim 8, wherein the dimension of said info-opening along the direction of said second address-selection line is larger than the width of said first address-selection line.

15. The 3D-MPROM according to claim 8, wherein the dimension of said info-opening along the direction of said first address-selection line is larger than the width of said second address-selection line.

16. A three-dimensional mask-programmable read-only memory (3D-MPROM), including at least first and second memory levels, comprising:

a first address-selection line;

a first config-dielectric located above said first address-selection line and comprising at least a first info-opening;

a second address-selection line located above said first config-dielectric;

a second config-dielectric located above said second address-selection line and comprising at least a second info-opening;

a third address-selection line located above said second config-dielectric;

whereby said first and second memory levels share said second address-selection line for address-selecting.

17. The 3D-MPROM according to claim 16, wherein the dimension of said first info-opening along the direction of said second address-selection line is larger than the width of said first address-selection line.

18. The 3D-MPROM according to claim 16, wherein the dimension of said first info-opening along the direction of said first address-selection line is larger than the width of said second address-selection line.

19. The 3D-MPROM according to claim 16, wherein the dimension of said second info-opening along the direction of said third address-selection line is larger than the width of said second address-selection line.

20. The 3D-MPROM according to claim 16, wherein the dimension of said second info-opening along the direction of said second address-selection line is larger than the width of said third address-selection line.