Three-dimensional integrated circuit structure

• US 20070077694A1
• Filed: 11/30/2006
• Published: 04/05/2007
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Granted Patent: US 7,888,764 B2
• Time in Patent Office: Days
• US Class Current: 438/152
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A semiconductor structure includes an interconnect region and a semiconductor stack bonded to the interconnect region through a bonding region. The stack includes at least two semiconductor layers having different electrical properties. The stack also includes single crystalline semiconductor material. The stack can be processed to form a mesa structure and the mesa structure can be processed to from a vertically oriented semiconductor device.

Claims

1. An apparatus, comprising:

an interconnect region; and

a multilayer semiconductor structure bonded to the interconnect region with a bonding region, the structure including at least two semiconductor layers having different electrical properties.

2. The apparatus of claim 1, wherein a surface of the structure defines a cleaved or planarized surface.

3. The apparatus of claim 1, wherein the bonding region includes a metal layer bonded to a semiconductor layer.

4. The apparatus of claim 1, wherein the structure includes single crystal semiconductor material.

5. The apparatus of claim 1, wherein the interconnect region includes aluminum or copper.

6. The apparatus of claim 1, wherein the structure includes at least two semiconductor layers having opposite conductivity types.

7. The apparatus of claim 1, wherein the structure includes two adjacent semiconductor layers having the same conductivity type.

8. The apparatus of claim 1, wherein the structure includes a sidewall which extends between a surface and an opposed surface of the structure.

9. The apparatus of claim 1, wherein the bonding region includes two metal layers with a bonding interface between them.

10. An apparatus, comprising:

a substrate which carries an electronic circuit and an interconnect region; and

a vertically oriented semiconductor device bonded to the interconnect region through a bonding region, the semiconductor device including a mesa structure having a pn junction.

11. The apparatus of claim 10, wherein the bonding region includes a metal layer.

12. The apparatus of claim 10, wherein opposed surfaces of the mesa structure include planarized surfaces.

13. The apparatus of claim 10, wherein the interconnect region includes a conductive line, the electronic circuit and vertically oriented semiconductor device being in communication with each other through the conductive line.

14. The apparatus of claim 10, wherein the vertically oriented semiconductor device is operated in response to a signal provided by the electronic circuit.

15. The apparatus of claim 10, wherein the mesa structure includes crystalline semiconductor material.

16. The apparatus of claim 10, wherein the vertically oriented semiconductor device includes a control terminal which adjusts the conductivity of the mesa structure in response to a signal from the electronic circuit.

17. A method, comprising:

providing an interconnect region; and

bonding a multiple layer structure to the interconnect region.

18. The method of claim 17, further including processing the multiple layer structure to form a mesa structure bonded to the interconnect region.

19. The method of claim 18, further including processing the mesa structure to form a vertically oriented semiconductor device bonded to the interconnect region.

20. The method of claim 17, wherein the multiple layer structure includes single crystal semiconductor material.

21. A method, comprising:

providing an interconnect region carried by an electronic circuit;

providing a substrate which includes a support structure coupled to a multiple layer structure; and

bonding the multiple layer structure to the interconnect region.

22. The method of claim 21, wherein the multiple layer structure includes single crystal semiconductor material.

23. The method of claim 21, further including removing the support structure from the multiple layer structure so the multiple layer structure is carried by the interconnect region.

24. The method of claim 21, further including processing the multiple layer structure to form a mesa structure.