Multiple fin formation

• US 20070077743A1
• Filed: 09/30/2005
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Mathew, Leo, Rao, Rajesh
• Granted Patent: US 7,265,059 B2
• Time in Patent Office: Days
• US Class Current: 438/595
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A FinFET includes a plurality of semiconductor fins. Over a semiconductor layer, patterned features (e.g. of minimum photolithographic size and spacing) are formed. In one example of fin formation, a first set of sidewall spacers are formed adjacent to the sides of these patterned features. A second set of sidewall spacers of a different material are formed adjacent to the sides of the first set of sidewall spacers. The first set of sidewall spacers are removed leaving the second set of sidewall spacers spaced from the patterned features. Both the second set of sidewall spacers and the patterned features are used as a mask to an etch that leaves semiconductor fins patterned as per the second set of sidewall spacers and the patterned features. These resulting semiconductor fins, which have sub-lithographic spacings, are then used for channels of a FinFET transistor.

Claims

1. A method for forming a FinFET, comprising:

providing a semiconductor layer;

forming a first layer of a first material over the semiconductor layer;

patterning the first layer to form a patterned feature having a pair of sidewalls;

forming a pair of first sidewall spacers of a second material adjacent to the pair of sidewalls of the patterned feature;

forming a pair of second sidewall spacers of a third material that is a different type from the second material, wherein the pair of second sidewall spacers are adjacent to the pair of first sidewall spacers;

removing the pair of first sidewall spacers;

after removing the pair of first sidewall spacers, etching the semiconductor layer using the pair of second sidewall spacers and the patterned feature as a mask to leave semiconductor fins patterned as per the pair of second sidewall spacers and the patterned feature; and

wherein channels of the FinFET are implemented in the semiconductor fins.

2. The method of claim 1 further comprising trimming the patterned feature prior to the etching the semiconductor layer.

3. The method of claim 2, wherein the first material and the third material are of different types, and the trimming comprises applying an etchant that is selective between the first material and the third material.

4. The method of claim 3, further comprising

providing a second layer of a fourth material over the semiconductor layer prior to forming the first layer, whereby the forming the first layer over the semiconductor layer results in the first layer being on the second layer;

and wherein the etchant that is selective between the first and third materials is further characterized as being selective between the first material and the fourth material.

5. The method of claim 3, wherein the first material comprises silicon germanium, the third material comprises silicon nitride, and the semiconductor layer comprises silicon, and the etchant that is selective between the first material and third material comprises a wet etchant.

6. The method of claim 2, wherein the pair of second sidewall spacers has a first width and the trimming narrows the patterned feature to substantially the first width.

7. The method of claim 1, further comprising:

providing a second layer of a fourth material over the semiconductor layer prior to forming the first layer, whereby the forming the first layer over the semiconductor layer results in the first layer being on the second layer;

etching through the second layer by applying an etchant that is selective between the first material and the fourth material.

8. The method of claim 7 wherein the etchant that is selective between the first material and the fourth material is further characterized as being selective between the third material and the fourth material.

9. The method of claim 1, further comprising:

forming a gate dielectric on the semiconductor fins; and

forming a continuous gate electrode on the gate dielectric.

10. The method of claim 9, wherein:

a first end of a semiconductor fin of the semiconductor fins that is formed as per the patterned feature is continuous with a first elevated source/drain region; and

a second end of the semiconductor fin that is formed as per the patterned feature is continuous with a second elevated source/drain region;

the method further comprising;

epitaxially growing a semiconductor material between the first elevated source/drain region and first ends of semiconductor fins of the semiconductor fins that are formed as per the pair of second sidewall spacers; and

epitaxially growing the semiconductor material between the second elevated source/drain region and second ends of the semiconductor fins that are formed as per the pair of second sidewall spacers.

16. The method of claim 11, wherein:

the patterning the second layer is further characterized as forming a plurality of additional patterned features;

the forming the first and second sidewall spacers is further characterized as forming a plurality of additional first and second sidewall spacers adjacent to the plurality of additional patterned features;

the forming the third and fourth sidewall spacers is further characterized as forming a plurality of additional third and fourth sidewall spacers adjacent to the plurality of additional first and second sidewall spacers;

the removing the first and second sidewall spacers is further characterized as removing the plurality of additional first and second sidewall spacers;

the trimming the patterned feature is further characterized as trimming the plurality of additional patterned features;

the etching is further characterized as leaving additional fins patterned as per the plurality of additional patterned features and the plurality of additional third and fourth sidewall spacers; and

wherein additional channels of the FinFET are implemented in the additional fins.

11. A method for forming a FinFET, comprising:

providing a semiconductor device structure including a substrate layer and a semiconductor layer over the substrate layer;

forming a first layer of a first material over the semiconductor layer;

providing a second layer of a second material over the first layer;

patterning the second layer to form a patterned feature having a first sidewall and a second sidewall;

forming a first sidewall spacer adjacent to the first sidewall and a second sidewall spacer adjacent to the second sidewall, wherein the first and second sidewall spacers are of a third material;

forming a third sidewall spacer adjacent to the first sidewall spacer and a fourth sidewall spacer adjacent to the second sidewall spacer, wherein the third and fourth sidewall spacers are of a fourth material;

removing the first and second sidewall spacers;

trimming the patterned feature using an isotropic etch;

etching the semiconductor layer to leave semiconductor fins patterned as per the third and fourth sidewall spacers and the patterned feature;

wherein channels of the FinFET are implemented in the semiconductor fins.

12. The method of claim 11, wherein the trimming comprises applying a wet etchant.

13. The method of claim 11, wherein the second material comprises silicon germanium, the fourth material comprises nitride, and the wet etchant comprises hydrofluoric acid and ammonium hydroxide.

14. The method of claim 11, wherein the first material comprises oxide.

15. The method of claim 11 wherein the second material comprises silicon germanium, the first material comprises oxide, the fourth material comprises nitride, and the semiconductor layer comprises monocrystalline silicon.

17. The method of claim 11, wherein the trimming the patterned feature narrows the patterned feature to a width that is substantially the same as a width of the third sidewall spacer.

18. A method for forming a FinFET, comprising:

providing a semiconductor layer;

forming a first layer of a first material over the semiconductor layer;

patterning the first layer to form a patterned feature having a first sidewall;

forming a first sidewall spacer of a second material adjacent to the first sidewall;

forming a second sidewall spacer of a third material adjacent to the first sidewall spacer;

removing the first sidewall spacer;

etching the semiconductor layer using the second sidewall spacer and the patterned feature as a mask to form a first fin as per the first patterned feature and a second fin as per the second sidewall spacer; and

wherein a first channel of the FinFET is implemented in the first fin and a second channel of the FinFET is implemented in the second fin.

19. The method of claim 18, further comprising:

forming a second patterned feature simultaneously with forming the first patterned feature;

forming a third sidewall spacer adjacent to the second patterned feature simultaneously with forming the first sidewall spacer;

forming a fourth sidewall spacer adjacent to the third sidewall spacer simultaneously with forming the second sidewall spacer;

removing the third sidewall spacer simultaneously with removing the first sidewall spacer;

forming a third fin as per the second patterned feature and a fourth fin as per the fourth sidewall spacer simultaneously with forming the first and second fins; and

wherein a third channel of the FinFET is implemented in the third fin and a fourth channel of the FinFET is implemented in the fourth fin.

20. The method of claim 19, further comprising trimming the first and second patterned features with an etch prior to etching the semiconductor layer.