Method for manufacturing a semiconductor device having a stepped contact hole

• US 20070077774A1
• Filed: 09/29/2006
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Abandoned Application

• Current Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Yoshida, Kazuyoshi
• Application Number:
  US11/529,328
• Publication Number:
  US 20070077774A1
• Time in Patent Office: Days
• US Class Current: 438/758
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 2221/1057 in via holes or trenches
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug

Abstract

A process for forming a stepped contact hole includes: dry-etching a portion of a silicon oxide film using a mixed gas including carbon-rich fluorocarbon gas to form a first contact hole, forming a specific film on the sidewall of the first contact hole; dry-etching the remaining portion of the silicon oxide film at the bottom of the first contact hole by using the specific film as a mask to form a second contact hole extending from the first contact hole; and removing the specific film.

Claims

1. A method for manufacturing a semiconductor device comprising:

forming a dielectric film on an underlying structure including a semiconductor substrate;

etching said dielectric film in a first anisotropic dry etching step using a first gas including rare gas, oxygen gas and carbon-rich gas, which is richer than CF₄ in carbon content, and a photoresist mask as an etching mask to a specified depth of said dielectric film, to thereby form a first contact hole in said dielectric film;

depositing a specific film at least within said first contact hole by using a second gas as a source gas;

etching a first potion of said specific film on a bottom of said first contact hole selectively from a second portion of said specific film on a sidewall thereof in a second anisotropic dry etching step using a third gas as an etching gas, to expose said dielectric film through said bottom of said first contact hole;

etching said dielectric film exposed from said bottom of said first contact hole in a third anisotropic dry etching step using a fourth gas as an etching gas and said second portion of said specific film as an etching mask, to form a second contact hole extending stepwise from said first contact hole and exposing therefrom said underlying structure; and

removing said second portion of said specific film on said sidewall of said first contact hole.

2. The method according to claim 1, wherein said first gas includes a gas selected from the group consisting of fluorocarbons C₄F₈, C₅F₈, C₄F₆ and any gas which is richer than these fluorocarbons in carbon content.

3. The method according to claim 1, wherein said fourth gas has a composition substantially same as a composition of said first gas.

4. The method according claim 1, wherein said second gas is selected from the group consisting of a mixed gas including CF₄ and H₂, a CH₃F gas and a CH₂F₂ gas.

5. The method according to claim 1, Wherein said third gas includes O₂.

6. The method according to claim 1, wherein each of said first and second contact holes has substantially no tapered portion.

7. The method according to claim 1, wherein said underlying structure includes a contact plug aligned with said second contact hole as viewed normal to said semiconductor substrate, an insulating film embedding said contact plug, interconnect lines embedded by said insulating film, said second contact hole is not aligned with any of said interconnect lines as viewed normal to said semiconductor substrate.

8. The method according to claim 1, wherein said underlying structure includes a diffused region.

9. The method according to claim 1, wherein said photoresist mask includes KrF resist or ArF resist.

10. The method according to claim 1, wherein the steps of said etching and forming are performed in a single chamber without exposing said semiconductor device to atmospheric air.

11. The method according to claim 1, wherein said dielectric film is a silicon oxide film.

12. The method according to claim 1, wherein said dielectric film consecutively includes a first silicon oxide film, a silicon nitride film and a second silicon oxide film, as viewed from said underlying structure, and said specified depth corresponds to a depth of said silicon nitride film.