Configurable system for performing repetitive actions and method for configuring and operating same

• US 20070078661A1
• Filed: 11/14/2006
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: PortalPlayer Inc (NVIDIA Corporation)
• Inventors: Karakas, Ahmet, Sriram, Partha, Quan, Robert, Gnanapa, Bhagawan
• Granted Patent: US 8,990,280 B2
• Time in Patent Office: Days
• US Class Current: 704/501
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence
• CPC Class Codes: G10L 19/0212 using orthogonal transformation
• CPC Class Codes: G10L 25/27 characterised by the analysis technique

Abstract

In some embodiments, a data processing system including an operation unit including circuitry configurable to perform any selected one of a number of operations on data (e.g., audio data) and a configuration unit configured to assert configuration information to configure the operation unit to perform the selected operation. When the operation includes matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry, the configuration information preferably includes bits that determine signs of all but magnitudes of only a subset of the coefficients. When the operation includes successive addition and subtraction operations on operand pairs, the configuration information preferably includes bits that configure the operation unit to operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of a sequence of data value pairs. In some embodiments, the configuration information includes bits that configure the operation unit to operate in a non-consecutive (e.g., butterfly or bit-reversed) addressing mode to access memory locations having consecutive addresses in a predetermined non-consecutive sequence. Other aspects are audio encoders and decoders including any embodiment of, and configuration units and operation units for use in, any embodiment of the system, and methods performed during operation of any embodiment of the system or configuration or operation unit thereof.

Claims

1. An audio data processing system, including:

an operation unit including circuitry configurable to perform any selected one of a number of operations on audio data, including at least one operation that includes a matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry; and

a configuration unit coupled and configured to assert configuration information to the operation unit to configure the operation unit to perform the selected one of the operations, wherein the configuration unit is operable to assert configuration bits to the operation unit to configure the operation unit to perform the matrix multiplication, wherein the configuration bits determine signs of all of the coefficients but magnitudes of only a subset of the coefficients.

2. The system of claim 1, wherein the configuration bits are indicative of the magnitudes of the subset of the coefficients.

3. The system of claim 1, wherein the magnitudes of the subset of the coefficients are stored in a memory and the configuration bits determine addresses of said magnitudes in the memory.

4. The system of claim 3, also including the memory, and wherein the operation unit includes a DMA engine coupled to the memory and operable to read the magnitudes of the subset of the coefficients from locations of the memory having said addresses.

5. The system of claim 1, wherein the matrix consists of four coefficients, the subset consists of two of the coefficients, and the configuration bits include a configuration bit-field that specifies the signs of all the coefficients.

6. The system of claim 1, wherein the matrix consists of four coefficients, each of two of the four coefficients has a first absolute magnitude, each other one of the four coefficients has a second absolute magnitude, and the configuration bits determine the first absolute magnitude, the second absolute magnitude, and signs of all four of the coefficients.

7. The system of claim 1, wherein said circuitry of the operation unit has pipelined architecture.

8. The system of claim 1, wherein said system is a portable media player.

9. An audio data processing system, including:

an operation unit including circuitry configurable to perform any selected one of a number of operations on audio data, including at least one operation in which the operation unit performs successive addition and subtraction operations on each pair of operands of a sequence of operand pairs; and

a configuration unit coupled and configured to assert configuration information to the operation unit to configure said operation unit to perform the selected one of the operations, wherein the configuration unit is operable to assert to the operation unit configuration bits which configure the operation unit to access a sequence of pairs of data values and operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of the sequence of pairs of data values.

10. The system of claim 9, wherein at least some of the data values in the sequence of pairs of data values are stored in a memory and the configuration bits determine addresses of the data values that are stored in the memory.

11. The system of claim 10, also including the memory, and wherein the operation unit includes a DMA engine coupled to the memory and operable to read the data values that are stored in the memory from locations of said memory having said addresses.

12. The system of claim 9, wherein said circuitry of the operation unit has pipelined architecture.

13. The system of claim 9, wherein said system is a portable media player.

14. An audio data processing system, including:

an operation unit including circuitry configurable to perform any selected one of a number of operations on audio data, including at least one operation that includes repetitive tasks, wherein the circuitry is configured to access a memory to read data from the memory and write data to the memory; and

a configuration unit coupled and configured to assert configuration information to the operation unit to configure said operation unit to perform the selected one of the operations, wherein the configuration unit is operable to assert configuration bits to the operation unit to configure the operation unit to operate in a non-consecutive addressing mode to access memory locations of the memory having consecutive addresses in a predetermined non-consecutive sequence.

15. The system of claim 14, wherein the non-consecutive addressing mode is a butterfly addressing mode in which the operation unit reads N elements of a data vector stored in memory locations of the memory having consecutive addresses, from a sequence of the memory locations having a predetermined non-consecutive sequence of addresses.

16. The system of claim 15, wherein the data vector is a vector X(k), where 0≦

k≦

N−

1, N is an even number greater than six, and the operation unit in the butterfly addressing mode reads the elements of the data vector in the sequence X(0), X(N−

1), X(1), X(N−

2), . . . , X(N/2−

2), X(N−

(N/2−

1)), X(N/2−

1), and X(N−

N/2), and then X(N−

N/2), X(N/2<

1), X(N−

(N/2−

1)), X(N/2−

2), . . . , X(N−

2), X(1), X(N−

1), and X(0).

17. The system of claim 15, wherein the data vector is a vector X(k) consisting of N complex elements, each of the complex elements having a real part and an imaginary part stored in memory locations having consecutive addresses, and the operation unit in the butterfly addressing mode first reads all the real parts of the data vector'"'"'s elements and then reads all the imaginary parts of the data vector'"'"'s elements.

18. The system of claim 14, wherein the non-consecutive addressing mode is a bit-reversed addressing mode in which the operation unit reads N elements of a data vector stored in memory locations of the memory having consecutive addresses, from a sequence of the memory locations having a predetermined non-consecutive sequence of addresses.

19. The system of claim 18, wherein the data vector is a vector X(k) consisting of N complex elements, where 0≦

k≦

N−

1, N=8, and each of the complex elements has a real part Re(X(k)) and an imaginary part Im(X(k)) stored in memory locations having consecutive addresses, and wherein the operation unit in the bit-reversed addressing mode reads the elements of the data vector in the sequence Re(X(0)), Im(X(0)), Re(X(4)), Im(X(4)), Re(X(2)), Im(X(2)), Re(X(6)), Im(X(6)), Re(X(1)), Im(X(1)), Re(X(5)), Im(X(5)), Re(X(3)), Im(X(3)), and Re(X(7)), Im(X(7)).

20. The system of claim 18, wherein the data vector is a vector X(k) consisting of N complex elements, where 0≦

k≦

N−

1, N=8, and each of the complex elements has a real part Re(X(k)) and an imaginary part Im(X(k)) stored in memory locations having consecutive addresses, and wherein the operation unit in the bit-reversed addressing mode reads the elements of the data vector in the sequence Re(X(0)), Re(X(4)), Re(X(2)), Re(X(6)), Re(X(1)), Re(X(5)), Re(X(3)), Re(X(7)), Im(X(0)), Im(X(4)), Im(X(2)), Im(X(6)), Im(X(1)), Im(X(5)), Im(X(3)), and Im(X(7)).

21. The system of claim 14, wherein the operation unit includes configurable address generation circuitry and can be configured to operate in any selected one of a number of non-consecutive addressing modes, the configuration bits configure the operation unit to operate in one of the non-consecutive addressing modes by specifying a vector size and said one of the non-consecutive addressing modes, and the operation unit in said one of the non-consecutive addressing modes reads, from the memory locations, elements of a data vector having the vector size.

22. The system of claim 21, wherein the configurable address generation circuitry includes address offset circuitry operable in each of the non-consecutive addressing modes to assert a predetermined sequence of offset values that determines a sequence of translated addresses in response to each base address of a data vector having the vector size to be read from the memory locations, and the configuration bits determine the predetermined sequence of offset values.

23. The system of claim 14, wherein the operation unit includes configurable address generation circuitry and can be configured to operate in any selected one of a number of non-consecutive addressing modes, the configuration bits configure the operation unit to operate in one of the non-consecutive addressing modes by specifying a vector size and said one of the non-consecutive addressing modes, and the operation unit in said one of the non-consecutive addressing modes writes, to the memory locations, elements of a data vector having the vector size.

24. The system of claim 23, wherein the configurable address generation circuitry includes address offset circuitry operable in each of the non-consecutive addressing modes to assert a predetermined sequence of offset values that determines a sequence of translated addresses in response to each base address of a data vector having the vector size to be written to the memory locations, and the configuration bits determine the predetermined sequence of offset values.

25. The system of claim 14, wherein said circuitry of the operation unit has pipelined architecture.

26. The system of claim 14, wherein said system is a portable media player.

27. A data processing system, including:

an operation unit including circuitry configurable to perform any selected one of a number of operations on data, including at least one of a T/F transform and an F/T transform on the data that includes a matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry; and

a configuration unit coupled and configured to assert configuration information to the operation unit to configure the operation unit to perform the selected one of the operations, wherein the configuration unit is operable to assert configuration bits to the operation unit to configure the operation unit to perform the matrix multiplication, wherein the configuration bits determine signs of all of the coefficients but magnitudes of only a subset of the coefficients.

28. The system of claim 27, wherein the magnitudes of the subset of the coefficients are stored in a memory and the configuration bits determine addresses of said magnitudes in the memory.

29. The system of claim 28, also including the memory, and wherein the operation unit includes a DMA engine coupled to the memory and operable to read the magnitudes of the subset of the coefficients from locations of the memory having said addresses.

30. The system of claim 27, wherein the matrix consists of four coefficients, each of two of the four coefficients has a first absolute magnitude, each other one of the four coefficients has a second absolute magnitude, and the configuration bits determine the first absolute magnitude, the second absolute magnitude, and signs of all four of the coefficients.

31. The system of claim 27, wherein the circuitry is configurable to perform an MDCT on the data, and wherein the MDCT includes the steps of pre-modulating a first set of data values to generate pre-modulated data, performing an intermediate transform on the pre-modulated data to generate transformed data, and post-modulating the transformed data, and at least one of the steps of pre-modulating and post-modulating includes performance of the matrix multiplication.

32. The system of claim 27, wherein the circuitry is configurable to perform an inverse MDCT on the data, and wherein the inverse MDCT includes the steps of pre-modulating a first set of data values to generate pre-modulated data, performing an intermediate transform on the pre-modulated data to generate transformed data, and post-modulating the transformed data, and at least one of the steps of pre-modulating and post-modulating includes performance of the matrix multiplication.

33. The system of claim 27, wherein said circuitry of the operation unit has pipelined architecture.

34. A data processing system, including:

an operation unit including circuitry configurable to perform any selected one of a number of operations on data, including at least one of a T/F transform and an F/T transform on the data in which the operation unit performs successive addition and subtraction operations on each pair of operands of a sequence of operand pairs; and

a configuration unit coupled and configured to assert configuration information to the operation unit to configure said operation unit to perform the selected one of the operations, wherein the configuration unit is operable to assert to the operation unit configuration bits which configure the operation unit to access a sequence of pairs of data values and operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of the sequence of pairs of data values.

35. The system of claim 34, wherein at least some of the data values in the sequence of pairs of data values are stored in a memory and the configuration bits determine addresses of the data values that are stored in the memory.

36. The system of claim 35, also including the memory, and wherein the operation unit includes a DMA engine coupled to the memory and operable to read the data values that are stored in the memory from locations of said memory having said addresses.

37. The system of claim 34, wherein the circuitry is configurable to perform an MDCT on the data, and wherein the inverse MDCT includes the steps of pre-modulating a first set of data values to generate pre-modulated data, performing an intermediate transform on the pre-modulated data to generate transformed data, and post-modulating the transformed data, and the step of performing an intermediate transform includes performance of the successive addition and subtraction operations on each said pair of operands.

38. The system of claim 34, wherein the circuitry is configurable to perform an inverse MDCT on the data, and wherein the inverse MDCT includes the steps of pre-modulating a first set of data values to generate pre-modulated data, performing an intermediate transform on the pre-modulated data to generate transformed data, and post-modulating the transformed data, and the step of performing an intermediate transform includes performance of the successive addition and subtraction operations on each said pair of operands.

39. The system of claim 34, wherein said circuitry of the operation unit has pipelined architecture.

40. A data processing system, including:

an operation unit including circuitry configurable to perform any selected one of a number of operations on data, including at least one of a T/F transform and an F/T transform on the data that includes repetitive tasks, wherein the circuitry is configured to access a memory to read data from the memory and write data to the memory; and

a configuration unit coupled and configured to assert configuration information to the operation unit to configure said operation unit to perform the selected one of the operations, wherein the configuration unit is operable to assert configuration bits to the operation unit to configure the operation unit to operate in a non-consecutive addressing mode to access memory locations in the memory having consecutive addresses in a predetermined non-consecutive sequence.

41. The system of claim 40, wherein the non-consecutive addressing mode is a butterfly addressing mode in which the operation unit reads N elements of a data vector stored in memory locations of the memory having consecutive addresses, from a sequence of the memory locations having a predetermined non-consecutive sequence of addresses.

42. The system of claim 40, wherein the non-consecutive addressing mode is a bit-reversed addressing mode in which the operation unit reads N elements of a data vector stored in memory locations of the memory having consecutive addresses, from a sequence of the memory locations having a predetermined non-consecutive sequence of addresses.

43. The system of claim 40, wherein the circuitry is configurable to perform an MDCT on the data, and wherein the MDCT includes the steps of pre-modulating a first set of data values to generate pre-modulated data, performing an intermediate transform on the pre-modulated data to generate transformed data, and post-modulating the transformed data, and the configuration bits configure the operation unit to operate in the non-consecutive addressing mode during performance of the intermediate transform.

44. The system of claim 40, wherein the circuitry is configurable to perform an inverse MDCT on the data, and wherein the inverse MDCT includes the steps of pre-modulating a first set of data values to generate pre-modulated data, performing an intermediate transform on the pre-modulated data to generate transformed data, and post-modulating the transformed data, and the configuration bits configure the operation unit to operate in the non-consecutive addressing mode during performance of the intermediate transform.

45. The system of claim 40, wherein said circuitry of the operation unit has pipelined architecture.

46. A method for configuring an operation unit comprising circuitry having pipelined architecture, said method including the steps of:

(a) defining a multi-step operation to be performed by the operation unit, said operation including at least one matrix multiplication of a data vector and a matrix comprising X coefficients exhibiting symmetry, where X is a number;

(b) determining a sequence of configuration commands and configuration data for configuring the operation unit to perform the matrix multiplication; and

(c) asserting to the operation unit configuration bits, determined by the sequence of configuration commands and configuration data, thereby configuring the operation unit to perform the matrix multiplication, wherein the configuration bits determine signs of all X of coefficients but magnitudes of only Y of the coefficients, where Y is less than X.

47. The method of claim 46, wherein the multi-step operation defined in step (a) includes the step performing the matrix multiplication to multiply an audio data vector by said matrix.

48. The method of claim 46, wherein the multi-step operation defined in step (a) is one of a T/F transform and an F/T transform on data.

49. A method for configuring an operation unit comprising circuitry having pipelined architecture, said method including the steps of:

(a) defining a multi-step operation to be performed by the operation unit, said operation including steps of performing successive addition and subtraction operations on each pair of operands of a sequence of operand pairs;

(b) determining a sequence of configuration commands and configuration data for configuring the operation unit to access a sequence of pairs of data values and perform the successive addition and subtraction operations on said sequence of pairs of data values; and

(c) asserting to the operation unit configuration bits, determined by the sequence of configuration commands and configuration data, thereby configuring the operation unit to access the sequence of pairs of data values and operate in an alternating addition/subtraction mode to perform the successive addition and subtraction operations on each pair of data values of the sequence of pairs of data values.

50. The method of claim 49, wherein the multi-step operation defined in step (a) is one of a T/F transform and an F/T transform on data.

51. A method for configuring an operation unit comprising circuitry having pipelined architecture, said method including the steps of:

(a) defining an operation to be performed by the operation unit, said operation including performance of repetitive processing on a sequence of data values stored in a memory in memory locations having consecutive addresses;

(b) determining a sequence of configuration commands and configuration data for configuring the operation unit to access the sequence of data values and perform said repetitive processing thereon; and

(c) asserting to the operation unit configuration bits, determined by the sequence of configuration commands and configuration data, thereby configuring the operation unit to operate in a non-consecutive addressing mode to access the data values from a predetermined sequence of the memory locations having non-consecutive addresses.

52. The method of claim 51, wherein the multi-step operation defined in step (a) is one of a T/F transform and an F/T transform on data.

53. The method of claim 51, wherein the non-consecutive addressing mode is a butterfly addressing mode in which the operation unit reads N elements of a data vector stored in memory locations of the memory having consecutive addresses, from a sequence of the memory locations having a predetermined non-consecutive sequence of addresses.

54. The method of claim 51, wherein the non-consecutive addressing mode is a bit-reversed addressing mode in which the operation unit reads N elements of a data vector stored in memory locations of the memory having consecutive addresses, from a sequence of the memory locations having a predetermined non-consecutive sequence of addresses.