Packet Combiner for a Packetized Bus with Dynamic Holdoff time

• US 20070079044A1
• Filed: 10/03/2006
• Published: 04/05/2007
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Mandal, Manas, Kaul, Ashish, Tsu, William, Case, Colyn
• Granted Patent: US 7,526,593 B2
• Time in Patent Office: Days
• US Class Current: 710/310
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportunistic merging procedure is advantageously used that merges a first request with a later request if the first request and the later request are mergeable and are received within a holdoff period that is dynamically determined based on a level of bus activity; otherwise, requests can be transmitted without merging.

Claims

1. A bus interface device for transmitting data transfer requests from a plurality of clients as packets on a bus, the device comprising:

a queue configured to store a plurality of data transfer requests from the plurality of clients, each data transfer request specifying a target address range;

control logic configured to generate a send condition signal;

packet forming logic configured to form a packet, in response to the send condition signal, from at least one of the data transfer requests in the queue, the packet forming logic being further configured to combine two or more of the data transfer requests in the queue into one packet in the event that the two or more data transfer requests being combined specify respective target address ranges that are mergeable;

output logic coupled to the packet forming logic and configured to drive the packet onto the bus; and

dynamic holdoff timer logic coupled to the packet forming logic and the control logic and configured to determine a holdoff period for a next packet based on a level of bus activity and to detect expiration of the holdoff period,

the control logic being configured to generate the send condition signal in response to expiration of the holdoff period.

2. The bus interface device of claim 1 wherein the dynamic holdoff timer logic is further configured to receive size information for a formed packet from the packet forming logic and to dynamically update the holdoff period for the next packet based at least in part on the size information.

3. The bus interface device of claim 2 wherein the data transfer requests are read requests and wherein the size information represents an amount of data requested by the formed packet.

4. The bus interface device of claim 3 wherein the dynamic holdoff timer logic is further configured to determine the holdoff period for the next packet based at least in part on a return transfer time associated with the amount of data requested by the formed packet.

5. The bus interface device of claim 2 wherein the data transfer requests are write requests and wherein the size information represents an amount of write data included in the formed packet.

6. The bus interface device of claim 5 wherein the dynamic holdoff timer logic is further configured to determine the holdoff period for the next packet based at least in part on a transfer time associated with the amount of write data included in the formed packet.

7. The bus interface device of claim 1 wherein the respective target address ranges specified by two or more data transfer requests are mergeable in the event that the respective target address ranges are contiguous.

8. The bus interface device of claim 7 wherein the respective target address ranges specified by two or more data transfer requests are mergeable in the event that the target address range of an older of the two or more data requests is below a target address range of a newer of the two or more data requests.

9. The bus interface device of claim 7 wherein the respective target address ranges specified by two or more data transfer requests are mergeable in the event that the target address range of an older of the two or more data requests is above a target address range of a newer of the two or more data requests.

10. The bus interface device of claim 1 further comprising:

unmergeable request detection logic coupled to the queue and the control logic, the unmergeable request detection logic being configured to determine whether an oldest data transfer request in the queue satisfies an unmergeability criterion,

wherein the control logic is further configured to generate the send condition signal in the event that the oldest data transfer request satisfies the unmergeability criterion.

11. A method for transmitting data transfer requests from a plurality of clients as packets on a bus, the method comprising:

receiving a first data transfer request specifying a first address range;

detecting whether a holdoff time has elapsed since receiving the first packet, wherein the holdoff time is dynamically adjustable;

in the event that the holdoff time has elapsed, forming a packet for transmission on the bus, wherein forming the packet includes;

determining whether a subsequent data transfer request specifying a second address range mergeable with the first address range was received during the holdoff time;

in the event that a subsequent data transfer request specifying a mergeable second address range was received, merging the first data transfer request and the mergeable subsequent data transfer request into the packet, and

in the event that no subsequent data transfer request specifying a mergeable second address range was received during the holdoff time, including only the first data transfer request in the packet;

transmitting the packet onto the bus; and

adjusting, based on a level of bus activity, the holdoff time for a next packet to be formed.

12. The method of claim 11 wherein adjusting the holdoff time includes:

determining a delay time associated with the data transfer request; and

adding the delay time to a current holdoff time, thereby adjusting the holdoff time.

13. The method of claim 12 wherein determining the delay time includes:

determining a size parameter corresponding to an amount of data associated with the request; and

based on the size parameter, determining a time required to transfer the amount of data associated with the data transfer request via the bus.

14. The method of claim 12 wherein the first packet includes at least one read request and wherein the delay time is determined based at least in part on an amount of time needed to transfer a response packet including the requested data via the bus.

15. The method of claim 12 wherein the first packet includes at least one write request and wherein the delay time is determined based at least in part on an amount of time needed to transfer the write data via the bus.

16. The method of claim 12 wherein detecting whether the holdoff time has elapsed includes:

decrementing the holdoff time for each cycle of a clock associated with the bus; and

detecting whether the holdoff time is zero.

17. The method of claim 16 wherein detecting whether the holdoff time has elapsed further includes:

in the event that the holdoff time is zero, detecting whether the bus is available to transmit a request,

wherein the holdoff time has elapsed in the event that the holdoff time is zero and the bus is available to transmit a request.

18. A processor comprising:

a plurality of processing cores, each processing core configured to generate data transfer requests; and

a bus interface unit configured to receive data transfer requests from the processing cores and to transmit the data transfer requests as packets on a bus, the bus interface unit including;

a queue configured to store a plurality of data transfer requests from the plurality of clients, each data transfer request specifying a target address range;

control logic configured to generate a send condition signal;

packet forming logic configured to form a packet, in response to the send condition signal, from at least one of the data transfer requests in the queue, the packet forming logic being further configured to combine two or more of the data transfer requests in the queue into one packet in the event that the two or more data transfer requests being combined specify respective target address ranges that are mergeable;

output logic coupled to the packet forming logic and configured to drive the packet onto the bus; and

dynamic holdoff timer logic coupled to the packet forming logic and the control logic and configured to determine a holdoff period for a next packet based on a level of bus activity and to detect expiration of the holdoff period,

the control logic being configured to generate the send condition signal in response to expiration of the holdoff period.

19. The processor of claim 18 wherein the processor is a graphics processor and the bus interface unit is configured for use with a PCI-Express (PCI-E) bus.

20. The processor of claim 18 wherein the dynamic holdoff timer logic is further configured to receive size information for a formed packet from the packet forming logic and to dynamically update the holdoff period for the next packet based at least in part on the size information.

21. The processor of claim 20 wherein the data transfer requests are read requests and wherein the size information represents an amount of data requested by the formed packet.

22. The processor of claim 21 wherein the dynamic holdoff timer logic is further configured to determine the holdoff period for the next packet based on a return transfer time associated with the amount of data requested by the formed packet.

23. The processor of claim 20 wherein the data transfer requests are write requests and wherein the size information represents an amount of write data included in the formed packet.

24. The processor of claim 23 wherein the dynamic holdoff timer logic is further configured to determine the holdoff period for the next packet based at least in part on a transfer time associated with the amount of write data included in the formed packet.