Power-up implementation for block-alterable memory with zero-second erase time

• US 20070079055A1
• Filed: 09/30/2005
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Li, Bo, Chandramouli, Subramanyam, Babb, Edward
• Granted Patent: US 7,500,081 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers

Abstract

A block-alterable memory, e.g., a flash memory, having substantially zero erase time is coupled to host. The block-alterable memory includes a controller that reads block information from the memory on power up to determine if a block of the memory is usable. The controller updates block map latches only if the block is usable. The controller also updates block status latches according to the block information. Thus, information about each block of the memory is easily accessible in the latches when the block alterable memory becomes ready for use on power up.

Claims

1. A method comprising:

reading block information from a block-alterable memory on power up of the memory;

determining if a block of the block-alterable memory is usable; and

updating address mapping information for the block only if the block is usable.

2. The method of claim 1 wherein determining if a block is usable further comprises:

determining if the block is one of bad and dirty.

3. The method of claim 1 wherein updating address mapping information further comprises:

updating the address mapping information after an internal voltage of the block alterable memory reaches a minimum level and an internal charging process is completed.

4. The method of claim 1 wherein updating address mapping information further comprises:

storing all of logical addresses and corresponding physical addresses of the block alterable memory in a volatile memory.

5. The method of claim 1 further comprising:

updating block status for the block in a volatile memory.

6. The method of claim 5 wherein updating block status further comprises:

marking one of a dirty status, an available status, and a bad status for each of physical blocks of the block alterable memory.

7. The method of claim 5 further comprising:

completing the power up of the block alterable memory after the updating of address mapping information and the updating of block status.

8. An apparatus comprising:

a block-alterable memory including

mapping latches to store address mapping information; and

a controller coupled to the memory and the mapping latches to;

read block information from the block-alterable memory on power up of the memory;

determine if a block of the block-alterable memory is usable; and

update the mapping latches only if the block is usable.

9. The apparatus of claim 8 wherein the controller further comprises:

a status decision unit to determine if the block is one of bad and dirty.

10. The apparatus of claim 8 wherein the mapping latches further comprise:

storage elements to store all of logical addresses and corresponding physical addresses of the block alterable memory.

11. The apparatus of claim 8 further comprising:

block status latches to record a status of the block.

12. The apparatus of claim 11 wherein the block status latches further comprise:

storage elements to store at least a dirty status field, an available status field, and a bad status field for each of physical blocks of the block alterable memory.

13. The apparatus of claim 8 further comprising:

an internal latch update signal generator coupled to the controller to generate a pulse to trigger the updating of the mapping latches, wherein the pulse is generated after an internal voltage reaches a maximum level and an internal charging process is completed.

14. A system comprising:

a block-alterable memory including;

mapping latches to store address mapping information;

a controller coupled to the memory and the mapping latches to;

read block information from the block-alterable memory on power up of the memory;

determine if a block of the memory is usable; and

update the mapping latches only if the block is usable; and

a battery-operated host in communication to the block-alterable memory.

15. The system of claim 14 wherein the controller further comprises:

a status decision unit to determine if the block is one of bad and dirty.

16. The system of claim 14 wherein the mapping latches further comprise:

storage elements to store all of logical addresses and corresponding physical addresses of the block alterable memory.

17. The system of claim 14 further comprising:

block status latches to record a status of the block.

18. The system of claim 17 wherein the block status latches further comprise:

storage elements to store at least a dirty status field, an available status field, and a bad status field for each of physical blocks of the block alterable memory.

19. The system of claim 14 further comprising:

an internal latch update signal generator coupled to the controller to generate a pulse to trigger the updating of the mapping latches, wherein the pulse is generated after an internal voltage reaches a maximum level and an internal charging process is completed.