Providing cache coherency in an extended multiple processor environment

• US 20070079075A1
• Filed: 09/29/2006
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Abandoned Application

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Church, Craig, Collier, Josh, Schibinger, Joseph
• Application Number:
  US11/540,886
• Publication Number:
  US 20070079075A1
• Time in Patent Office: Days
• US Class Current: 711/141
• CPC Class Codes: G06F 12/082 Associative directories G06F12/0822 takes precedence
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831
• CPC Class Codes: G06F 12/0826 Limited pointers directories; State-only directories without pointers
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 2212/1048 Scalability

Abstract

A method and system for scaling upwards a multiprocessor cache coherency scheme includes at least two cells. Each cell containing a multiple processor assembly, a cache coherency director, and a system controller. The cache coherency director include an intermediate home agent (IHA) and an intermediate cache agent (ICA). An IHA in one cell communicates with an ICA in another cell to arbitrate the availability of lines of cache that are requested by a processor in one of the cells. A protocol that includes request retries avoids system lockups is used as the basis for inter-cell cache coherency communication.

Claims

1. A system for maintaining cache coherency in multiprocessor environment, the system comprising:

a first multiprocessor assembly comprising at least two processors, each processor having local cache to store at least one cache line;

a first coherency director (CD) comprising a first intermediate home agent (IHA) and a first intermediate cache agent (ICA), wherein the CD is coupled to the first multiprocessor assembly;

a first remote directory coupled to the CD, wherein the remote directory stores cache location information;

a first memory providing cache data to the first processor assembly;

wherein the first multiprocessor assembly, the first CD, the first remote directory, and the first memory comprise a first cell;

a second cell having a second multiprocessor assembly, a second CD, a second remote directory, and a second memory, wherein the second CD comprises a second IHA and a second ICA; and

interconnections between the first IHA and the second ICA and between the second IHA and the first ICA, wherein requests and responses for cache information are communicated between the first cell and the second cell such that the first IHA of the first cell requests cache information from the second ICA of the second cell and the second IHA of the second cell requests cache information from the first ICA of the first cell.

2. The system of claim 1, further comprising a first system controller and a second system controller, wherein respective system controllers coordinate events within each cell.

3. The system of claim 1, wherein the first and second memory comprise one or more of a centralized memory and a distributed memory.

4. The system of claim 1, wherein the requests for cache information communicated between the first cell and the second cell comprise requests to read cache status and data.

5. The system of claim 1, wherein the responses for cache information communicated between the first cell and the second cell comprise a retry request if the responding cell is unable to provide the information requested.

6. The system of claim 1, wherein the first remote directory stores cache location and status information for lines of cache that are associated with the first processor assembly which are being used by processors of the second cell.

7. A method of obtaining a line of cache in a cache coherent multiprocessor system comprising at least two cells of multiprocessor assemblies, the method comprising:

requesting a line of cache from a first processor in a first multiprocessor assembly in a first cell, the request being sent to an intermediate home agent (IHA) of the first cell;

reading a location of the requested line of cache from a remote directory in the first cell;

sending the request for the line of cache from the IHA of the first cell to an intermediate cache agent (ICA) of a second cell;

transferring the request for the line of cache from the ICA of the second cell to the IHA of the second cell;

snooping the processors of the second cell for the requested line of cache, wherein processors in the second cell respond to the request by returning status to the IHA of the second cell;

making the line of cache available for use;

sending response information from the second cell to the first cell where the ICA of the second cell communicates with the IHA of the first cell;

receiving the requested cache information by the first cell and transferring the information to the first processor of the first cell, whereby the line of cache information is available to fill the request of the first processor in the first cell.

8. The method of claim 7, further comprising:

updating the remote directory information of the first cell to indicate that the line of cache is no longer held by the second cell.

9. The method of claim 7, further comprising:

retrying the step of sending the request for the line of cache from the IHA of the first cell to the ICA of the second cell if the second cell indicates unavailability.

10. The method of claim 9, wherein the step of retrying is executed after a predetermined interval.

11. The method of claim 10, wherein the predetermined interval is provided by the second cell in response to a first send request to the IHA of the second cell.

12. The method of claim 7, wherein snooping the processors of the second cell comprises sending out requests for the line of cache to each processor in the second cell.

13. The method of claim 7, wherein making the line of cache available for use comprises releasing the requested line of cache by writing back the line of cache into memory and responding that the line of cache is available.

14. The method of claim 7, wherein sending the request for the line of cache from the IHA of the first cell to an intermediate cache agent (ICA) of a second cell comprises sending the request to the ICA of the second cell, wherein the ICA of the second cell comprises a batch processing mechanism.

15. The method of claim 14, wherein the batch processing mechanism assigns all incoming requests in arrival order and processes the requests in batch order.

16. The method of claim 15, wherein the batch order comprises processing request from two consecutive batches simultaneously.