MCU with power saving mode

• US 20070079148A1
• Filed: 09/30/2005
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Holberg, Douglas, Pastorello, Douglas, Chowdhury, Golam, Sahu, Biranchinath, Durbin, William
• Granted Patent: US 7,441,131 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.

Claims

1. A microcontroller unit, comprising:

a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit;

control logic responsive to the first control signal for generating an enable signal at a first level and responsive to a second control signal for generating the enable signal at a second level; and

a voltage regulator for generating a regulated voltage from an input voltage, the voltage regulator shutting down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powering up to provide an regulated voltage at an operating level responsive to the enable signal at the second level.

2. The microcontroller unit of claim 1, wherein the control logic further comprises:

first logic circuitry for generating a third control signal responsive to the first control signal from the processor;

second logic circuitry for generating a fourth control signal responsive to the second control signal from the processor; and

a latch for generating the enable signal at first level responsive to the third control signal and for generating the enable signal at the second level responsive to the fourth control signal.

3. The microcontroller unit of claim 2, further including a third logic circuit for generating a hold signal to digital components of the microcontroller unit responsive to the first control signal and the enable signal of the latch.

4. The microcontroller unit of claim 3, wherein the first logic further includes:

a level shifter for shifting the a voltage level of the first control signal from a first level to a second level, an output of the level shifter provided to the third logic circuit; and

a filter for delaying an input of an application of the shifted first control signal to the latch until after the third logic circuit generates the hold signal responsive to the output of the level shifter.

5. The microcontroller of claim 4, wherein the level shifter maintains a zero volt output while the voltage regulator is shut down.

6. The microcontroller of claim 4, wherein the filter prevents noise from turning off the voltage regulator.

7. The microcontroller of claim 1, further including;

at least one digital device powered by the regulated voltage and entering a powered down mode responsive to the voltage regulator shutting down, the at least one digital device providing at least one digital output signal; and

an input/output cell connected to receive the digital output signal and a hold signal, the input/output cell maintaining a last state of the digital output signal responsive to the hold signal when the at least one digital device is in the powered down state.

8. The microcontroller unit of claim 7, wherein the input/output cell further comprises:

a level shifter for shifting the level of the digital output signal to a desired level for an analog device; and

hold logic for maintaining the last state of the shifted digital output signal in the last state responsive to the hold signal.

9. The microcontroller unit of claim 7, wherein the input/output cell further comprises:

a pair of inverter circuits connected in series;

a first switch for connecting and disconnecting the digital output signal to the pair of inverter circuits responsive to the hold signal;

a feedback loop connected between an output of the pair of inverter circuits and an input of the pair of inverter circuits; and

a second switch for opening and closing the feedback loop between the output and the input of the pair of inverter circuits responsive to the hold signal.

10. The microcontroller unit of claim 9, wherein the first switch is closed and the second switch is open responsive to the hold signal in a first state and the first switch is open and the second switch is closed responsive to the hold signal in a second state.

11. A microcontroller unit, comprising:

a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit;

control logic responsive to the first control signal for generating an enable signal at a first level and responsive to a second control signal for generating the enable signal at a second level;

a voltage regulator for generating a regulated voltage from an input voltage, the voltage regulator shutting down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powering up to provide an regulated voltage at an operating level responsive to the enable signal at the second level;

at least one digital device powered by the regulated voltage and entering a powered down mode responsive to the voltage regulator shutting down, the at least one digital device providing at least one digital output signal; and

an input/output cell connected to receive the digital output signal and a hold signal, the input/output cell maintaining a last state of the digital output signal responsive to the hold signal when the at least one digital device is in the powered down state.

12. The microcontroller unit of claim 11, wherein the control logic further comprises:

first logic circuitry for generating a third control signal responsive to the first control signal from the processor;

second logic circuitry for generating a fourth control signal responsive to the second control signal from the processor; and

a latch for generating the enable signal at first level responsive to the third control signal and for generating the enable signal at the second level responsive to the fourth control signal.

13. The microcontroller unit of claim 12, further including a third logic circuit for generating the hold signal to digital components of the microcontroller unit responsive to the first control signal and the enable signal of the latch.

14. The microcontroller unit of claim 13, wherein the first logic further includes:

a level shifter for shifting the a voltage level of the first control signal from a first level to a second level, an output of the level shifter provided to the third logic circuit; and

a filter for delaying an input of an application of the shifted first control signal to the latch until after the third logic circuit generates the hold signal responsive to the output of the level shifter.

15. The microcontroller of claim 14, wherein the level shifter maintains a zero volt output while the voltage regulator is shut down.

16. The microcontroller of claim 14, wherein the filter prevents noise from turning off the voltage regulator.

17. The microcontroller unit of claim 11, wherein the input/output cell further comprises:

a level shifter for shifting the level of the digital output signal to a desired level; and

hold logic for maintaining the last state of the shifted digital output signal in the last state responsive to the hold signal.

18. The microcontroller unit of claim 11, wherein the input/output cell further comprises:

a pair of inverter circuits connected in series;

a first switch for connecting and disconnecting the digital output signal to the pair of inverter circuits responsive to the hold signal;

a feedback loop connected between an output of the pair of inverter circuits and an input of the pair of inverter circuits; and

a second switch for opening and closing the feedback loop between the output and the input of the pair of inverter circuits responsive to the hold signal.

19. The microcontroller unit of claim 18, wherein the first switch is closed and the second switch is open responsive to the hold signal in a first state and the first switch is open and the second switch is closed responsive to the hold signal in a second state.