Power-efficient technique for invoking a co-processor
First Claim
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1. A method of processing data in a computer system having a first processor and a second processor, the method comprising:
- instructing the second processor to perform an operation repeatedly on a data stream;
placing the first processor in a low power state; and
performing the operation repeatedly on the data stream with the second processor while the first processor remains in the low-power sleep mode.
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Abstract
Various embodiments are disclosed relating to power-efficient techniques for invoking a co-processor. In an example embodiment, a computer system may include a first processor (e.g., a host processor) and a second processor (e.g., a co-processor). The first processor may instruct the second processor to perform an operation repeatedly on a data stream. The first processor may be placed in a low power state. The second processor may perform the operation repeatedly on the data stream while the first processor remains in the low-power state.
67 Citations
20 Claims
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1. A method of processing data in a computer system having a first processor and a second processor, the method comprising:
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instructing the second processor to perform an operation repeatedly on a data stream;
placing the first processor in a low power state; and
performing the operation repeatedly on the data stream with the second processor while the first processor remains in the low-power sleep mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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receiving an instruction at a second processor from a first processor, the instruction including a command field and an execution mode field, the execution mode field specifying one of a plurality of modes of execution including a regular mode indicating the instruction should be executed once, and a repeat mode indicating that the instruction may be executed repeatedly without further instructions from the first processor; and
executing the instruction based on the execution mode field.
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12. A computer system comprising:
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memory;
a first processor; and
a second processor, wherein the first processor is configured to instruct the second processor to perform repeatedly an operation on a data stream and to enter a low power state after instructing the second processor to perform repeatedly the operation. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification