Integrated Circuit Testing Module Including Signal Shaping Interface

• US 20070079204A1
• Filed: 10/25/2006
• Published: 04/05/2007
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Inapac Technology Incorporated (Rambus Inc.)
• Inventors: Ong, Adrian
• Granted Patent: US 8,001,439 B2
• Time in Patent Office: Days
• US Class Current: 714/738
• CPC Class Codes: G01R 31/31928 Formatter driver, receiver details G01R31/31924
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. In order to do so, the testing interface includes components configured for generating addresses, commands, and test data to be conveyed to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent. The systems are optionally configured to include a test plan memory component configured to store one or more test plans. A test plan may include a sequence of test patterns and/or conditional branches whereby the tests to be performed next are dependent on the results of the preceding tests. The test plan memory is, optionally, be detachable from the test module.

Claims

1. A system comprising:

one or more input components configured to receive signals having a first slew rate from an automated testing equipment configured to test an integrated circuit;

one or more data generating components configured to generate test signals responsive to the signals received from the automated testing equipment; and

one or more output components configured to convey the generated test signals to the integrated circuit at a second slew rate, the integrated circuit being detachable from the one or more output components, the second slew rate being faster than the first slew rate.

2. The system of claim 1, further including a command generating component.

3. The system of claim 2, wherein the command generating component is configured to generate a command responsive to a test plan.

4. The system of claim 1, wherein the one or more data generating components are further configured to generate the test signals responsive to an address.

5. The system of claim 1, further including an address generating component.

6. The system of claim 5, wherein the address generating component and the one or more data generating components are detachable from the automated testing equipment.

7. The system of claim 1, further including a clock adjustment component configured to generate an adjustment between a clock signal sent to the integrated circuit and a clock signal used to determine when to expect data from the integrated circuit.

8. The system of claim 7, wherein the adjustment is responsive to the signals received from the automated testing equipment.

9. The system of claim 1, further comprising a test plan memory component configured for storing at least one test plan, the one or more data generating components further configured to generate test signals responsive to the one or more test plans.

10. The system of claim 9, wherein the test plan memory component is detachable from the one or more data generating components.

11. The system of claim 1, wherein the one or more input components are configured to receive the signals from the automated testing equipment at a first clock frequency, and the one or more output components are configured to convey the generated test signals to the integrated circuit at a second clock frequency higher than the first clock frequency.

12. The system of claim 11, further comprising one or more data receiving components configured to receive data from the integrated circuit at the second clock frequency and to communicate to the automated testing equipment in response to the received data at the first clock frequency.

13. The system of claim 11, wherein the one or more data receiving components are configured to compress the received data using a test plan.

14. The system of claim 11, wherein the one or more data receiving components are configured to compare the received data to an expected result responsive to a test plan.

15. The system of claim 1, wherein the one or more input components and the one or more output components are included in a test module, the test module being one of a plurality of test modules included in a test array configured for testing a plurality of integrated circuits, the test array including a memory configured to store one or more test plans for testing the plurality of integrated circuits, the memory being shared by the plurality of test modules.

16. The system of claim 1, wherein the integrated circuit is a memory device.

17. The system of claim 1, further including the integrated circuit.

18. A method comprising:

attaching an automated testing equipment to a test module having a clock synchronization component;

attaching an integrated circuit to be tested to the test module;

receiving signals having a first slew rate from the automated testing equipment at the test module;

generating test signals within the test module responsive to the signals received from the automated testing equipment; and

sending the generated test signals to the integrated circuit at a second slew rate faster than the first slew rate.

19. The method of claim 18, wherein the signals received from the automated testing equipment include a signal to generate an adjustment between a clock signal sent to the integrated circuit and a clock signal used to determine when to expect data from the integrated circuit.

20. The method of claim 18, wherein the signals received from the automated testing equipment include a signal to select at least one test plan, used to generate the test signals to be sent to the integrated circuit, from a test plan memory component including the at least one test plan.

21. The method of claim 20, wherein the test plan memory component is detachable from the test module.

22. The method of claim 18, further comprising

receiving the signals from the automated testing equipment at the test module at a first clock frequency, and

sending the generated test signals to the integrated circuit at a second clock frequency higher than the first clock frequency.

23. The method of claim 22, further comprising

receiving signals from the integrated circuit at the second clock frequency, the received signals being responsive to the test signals sent to the integrated circuit, and

sending a communication from the test module to the automated testing equipment in response to the signals received from the integrated circuit.

24. The method of claim 18, further comprising detaching the test module from the integrated circuit, and attaching a second integrated circuit to the test module to test the second integrated circuit.

25. An integrated circuit tested using the method of claim 18.

26. A system comprising:

means for receiving signals having a first slew rate from an automated testing equipment at a test module;

means for generating test signals within the test module responsive to the signals received from the automated testing equipment; and

means for sending the generated test signals to an integrated circuit to be tested at a second slew rate faster than the first slew rate.