OUTPUT BUFFER CIRCUIT
First Claim
1. An output buffer circuit with a compensation capacitive load, comprising:
- an input part having two input terminal receiving differential input voltage signals;
an output part increasing a gain of the differential input voltages;
a current source biasing the output part; and
a slew rate increasing part connected to the output part and the compensation capacitive load, the slew rate increasing part including a switching element to increase a slew rate of the output buffer circuit.
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Accused Products
Abstract
Provided is an output buffer circuit having a slew rate increasing part configured with a switching element. The output buffer circuit can obtain an output voltage having a high slew rate even though a smaller amount of a bias current than that required in a conventional output buffer is used. Therefore, the output buffer circuit can reduce power consumption. In the output buffer circuit with a compensation capacitive load, an input part has two input terminal receiving differential input voltage signals, and an output part increases a gain of the differential input voltages. A current source biases the output part, and a slew rate increasing part is connected to the output part and the compensation capacitive load. The slew rate increasing part includes a switching element to increase a slew rate of the output buffer circuit.
16 Citations
22 Claims
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1. An output buffer circuit with a compensation capacitive load, comprising:
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an input part having two input terminal receiving differential input voltage signals;
an output part increasing a gain of the differential input voltages;
a current source biasing the output part; and
a slew rate increasing part connected to the output part and the compensation capacitive load, the slew rate increasing part including a switching element to increase a slew rate of the output buffer circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An output buffer circuit with a compensation capacitive load, comprising:
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an input part having two input terminals receiving differential input voltage signals;
an output part increasing a gain of the differential input voltages;
a floating current source biasing the output part;
a summing circuit connected to the input part and the floating current source, the summing circuit being configured to sum a current supplied from the input part and an internal current supplied from the floating current source; and
a slew rate increasing part connected to the input part and the summing circuit, the slew rate increasing part including a plurality of switching elements to increase a slew rate of the output buffer circuit. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification