Multi-chip semiconductor memory device having internal power supply voltage generation circuit for decreasing current consumption
First Claim
1. A multi-chip semiconductor memory device, comprising a plurality of memory chips sharing a predetermined chip enable signal, each of the plurality of memory chips comprising:
- an active internal power supply generation circuit configured to convert an external power supply voltage into an internal power supply voltage and to be disabled in response to deactivation of a predetermined drive control signal; and
a conversion control circuit for generating the drive control signal, wherein the drive control signal is deactivated in an interval in which any of the plurality of memory chips is in an active interval.
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Abstract
A multi-chip semiconductor memory device may comprise of a plurality of memory chips sharing a predetermined chip enable signal. Each of the plurality of memory chips may comprise of an active internal power supply generation circuit configured to convert an external power supply voltage into an internal power supply voltage and to be disabled in response to deactivation of a predetermined drive control signal. Each of the plurality of memory chips may also comprise of a conversion control circuit for generating the drive control signal, wherein the drive control signal is deactivated in an interval in which any of the plurality of memory chips is in an active interval.
115 Citations
14 Claims
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1. A multi-chip semiconductor memory device, comprising a plurality of memory chips sharing a predetermined chip enable signal, each of the plurality of memory chips comprising:
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an active internal power supply generation circuit configured to convert an external power supply voltage into an internal power supply voltage and to be disabled in response to deactivation of a predetermined drive control signal; and
a conversion control circuit for generating the drive control signal, wherein the drive control signal is deactivated in an interval in which any of the plurality of memory chips is in an active interval. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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- 9. A muti-chip semiconductor memory device, comprising a plurality of memory chips sharing a predetermined chip enable signal and each having an active internal power supply generation circuit which independently converts an external power supply voltage into an internal power supply voltage, wherein, while any of the plurality of memory chips is in an active interval, active internal power supply generation circuits of remaining memory chips are disabled.
Specification