System and method of on-circuit asynchronous communication, between synchronous subcircuits

• US 20070081414A1
• Filed: 04/06/2006
• Published: 04/12/2007
• Est. Priority Date: 09/12/2005
• Status: Abandoned Application

• Current Assignee: Qualcomm Technologies Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Boucard, Philippe, Douady, Cesar, Montperrus, Luc
• Application Number:
  US11/399,293
• Publication Number:
  US 20070081414A1
• Time in Patent Office: Days
• US Class Current: 365/189.150
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: G06F 2205/126 Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: G06F 7/00 Methods or arrangements for processing data by operating upon the order or content of the data handled logic circuits H03K19/00
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/005 Correction by an elastic buffer
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The system for on-circuit asynchronous communication, between synchronous subcircuits, includes a first synchronous subcircuit regulated by a first clock frequency, which sends requests to a second synchronous subcircut regulated by a second clock frequency. The first subcircuit transmits data to the second subcircuit through a first mesochronous unidirectional communication link, and the second subcircuit transmits availability tokens which report the availability of an additional elementary memory location in the queue situated at the extremity of the first mesochronous unidirectional communication link to the first subcircuit, via a second mesochronous unidirectional communication link. The first subcircuit comprises means of transmission for directly transmitting to the second subcircuit data of a size that is at most equal to the size corresponding to the elementary memory locations available in the queue.

Claims

1. System for on-circuit asynchronous communication, between synchronous subcircuits, comprising:

a first synchronous subcircuit regulated by a first clock frequency, suitable for sending requests to a second synchronous subcircuit regulated by a second clock frequency, the first subcircuit transmitting data to the second subcircuit through a first mesochronous unidirectional communication link, and the second subcircuit transmitting tokens to the first subcircuit through a second mesochronous unidirectional communication link;

wherein the first mesochronous unidirectional communication link comprises a memory organized as a queue situated at the end of communication of the first link, and wherein an elementary memory location of the queue has a predetermined size;

wherein the second synchronous subcircuit comprises sending means for transmitting to the first subcircuit availability tokens of an additional elementary memory location in the queue as soon as an elementary memory location of the queue is read by the second subsystem; and

the first subcircuit comprises means of transmission for transmitting directly to the second subcircuit data of a size at most equal to the size corresponding to the elementary memory locations available in the queue.

2. System according to claim 1, wherein the first subcircuit comprises means of determination of the number of elementary memory locations available, on the basis of the availability tokens.

3. System according to claim 1, wherein the queue is write-regulated by the first clock frequency, and read-regulated by the second clock frequency.

4. System according to claim 1, wherein the queue comprises a number of elementary memory locations, at least equal to the number of cycles of the clock having the lowest regulating frequency, allowing a transfer of data from the first subsystem to the second subsystem, and the transmission from the second subsystem to the first subsystem of a token of availability of an additional elementary memory location in the queue.

5. System according to claim 1, wherein a mesochronous unidirectional communication link comprises means of intermediate synchronization of the data transmitted by the link.

6. System according to claim 1, wherein a plurality of mesochronous unidirectional communication links, with the same direction, have a commonly transmitted clock regulating frequency.

7. System according to claim 1, further comprising means of testing of the system by a device for generating test vectors, the means of testing comprising means for rendering the queues synchronous.

8. System according to claim 2, further comprising means of stopping/starting the first and second subcircuits, the stopping/starting means comprising means of dispatching a signal representative of the activity of one of the subcircuits jointly with the respective signal representative of the clock regulating frequency of the subcircuit, means for resetting to zero the determined number of elementary memory locations available in the queue of the second subcircuit when the first subcircuit or the second subcircuit becomes inactive, and means for sending the number of availability tokens corresponding to the number of elementary memory locations available in the queue, when the first and second subcircuits are both active again.

9. Method of on-circuit asynchronous communication between synchronous subcircuits, the circuit comprising a first synchronous subcircuit regulated by a first clock frequency, suitable for sending requests to a second synchronous subcircuit regulated by a second clock frequency, the method comprising:

transmitting data from the first subcircuit to the second subcircuit through a first mesochronous unidirectional communication link, and transmitting tokens from the second subcircuit to the first subcircuit through a second mesochronous unidirectional communication link,

wherein the first mesochronous unidirectional communication link comprises a memory organized as a queue situated at the end of communication of the link, an elementary memory location of the queue having a predetermined size, the method further comprising transmitting an availability token for an additional elementary memory location in the queue to the first subcircuit as soon as an elementary memory location of the queue is read by the second subcircuit, and

transmitting data of a size at most equal to the size corresponding to the elementary memory locations available in the queue from the first subcircuit to the said second subcircuit.

10. Method according to claim 9, wherein the circuit is tested with a device for generating test vectors, rendering the queues synchronous.

11. Method according to claim 9, wherein the stopping/starting of the first and second subcircuits comprises:

dispatching a signal representative of the activity of one of the subcircuits jointly with the respective signal representative of the clock regulating frequency of the subcircuit;

resetting to zero the determined number of elementary memory locations available in the queue of the second subcircuit when the first subcircuit or the second subcircuit becomes inactive; and

sending the number of availability tokens corresponding to the number of elementary memory locations available in the queue, when the first and second subcircuits are both active again.

12. Use of the method according to claim 9 to perform a hierarchical partition of large circuits into small subcircuits with a simplified apportionment of time.