Semiconductor devices having transistors with vertical channels and method of fabricating the same

• US 20070082448A1
• Filed: 06/30/2006
• Published: 04/12/2007
• Est. Priority Date: 10/12/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Dong-gun, Lee, Kang-yoon, Seo, Hyeoung-won, Yoon, Jae-man, Kim, Seong-goo, Kim, Bong-soo
• Granted Patent: US 7,368,352 B2
• Time in Patent Office: Days
• US Class Current: 438/268
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4 F². The semiconductor device comprises: a cell array region having a plurality of unit cells, each unit cell having a cell occupation area, repeatedly aligned along a first direction and along a second direction, the first and second directions being perpendicular to each other in a horizontal direction along a primary surface of a semiconductor substrate, wherein each unit cell has a uniform first pitch in the first direction and in the second direction; an active pillar vertically extending from an active region of each unit cell integrally with the semiconductor substrate in a vertical direction that is perpendicular with respect to the primary surface of the semiconductor substrate, wherein widths of at least a portion of the active pillar in the first direction and in the second direction are equal to a first width 1 F as a minimum feature size in the cell array region; a ring-shaped gate surrounding a sidewall of the active pillar; a channel region formed to extend along the active pillar in the vertical direction; a buried bit line formed below the active pillar in the semiconductor substrate; and a word line extending in the horizontal direction perpendicular to the buried bit line, and electrically connected to the ring-shaped gate, wherein a distance from the active pillar of any one unit cell of the plurality of unit cells to each of the active pillars of nearest neighboring unit cells in the first direction and the second direction is equal to the first width of the active pillar of one unit cell.

Claims

1. A semiconductor device comprising:

a cell array region having a plurality of unit cells, each unit cell having a cell occupation area, repeatedly aligned along a first direction and along a second direction, the first and second directions being perpendicular to each other in a horizontal direction along a primary surface of a semiconductor substrate, wherein each unit cell has a uniform first pitch in the first direction and in the second direction;

an active pillar vertically extending from an active region of each unit cell integrally with the semiconductor substrate in a vertical direction that is perpendicular with respect to the primary surface of the semiconductor substrate, wherein widths of at least a portion of the active pillar in the first direction and in the second direction are equal to a first width 1 F as a minimum feature size in the cell array region;

a ring-shaped gate surrounding a sidewall of the active pillar;

a channel region formed to extend along the active pillar in the vertical direction;

a buried bit line formed below the active pillar in the semiconductor substrate; and

a word line extending in the horizontal direction perpendicular to the buried bit line, and electrically connected to the ring-shaped gate, wherein

a distance from the active pillar of any one unit cell of the plurality of unit cells to each of the active pillars of nearest neighboring unit cells in the first direction and the second direction is equal to the first width of the active pillar of one unit cell.

2. The semiconductor device of claim 1, wherein each of the plurality of unit cells has a cell occupation area of 4 F².

3. The semiconductor device of claim 1, wherein the bit line extends along either one direction of the first direction and the second direction with a uniform width.

4. The semiconductor device of claim 1, wherein the active pillar comprises an upper active portion having the first width in the first direction and the second direction, and a lower active portion having a smaller width than the first width in the first direction and the second direction, and

the ring-shaped gate is formed to surround a sidewall of the lower active portion of the active pillar.

5. The semiconductor device of claim 1, wherein the ring-shaped gate comprises an inner circumference surface about a sidewall of the lower active portion of the active pillar, and an outer circumference surface contacting the word line.

6. The semiconductor device of claim 1, further comprising a gate dielectric layer between the ring-shaped gate and the sidewall of the active pillar.

7. A semiconductor device comprising:

a cell array region having a plurality of unit cells, each unit cell having a cell occupation area in a semiconductor substrate;

an active pillar extending in a vertical direction with respect to the substrate from an active region of each unit cell in the cell array region, the active pillar having a first width portion and a second width portion, the second width portion having a width that is greater than a width of the first width portion;

a ring-shaped insulation spacer on a sidewall of the second width portion of the active pillar, the ring-shaped insulation spacer having an inner surface and an outer surface;

a gate dielectric layer on a sidewall of the active pillar;

a ring-shaped gate on a portion of the gate dielectric layer formed on the sidewall of the active pillar, the ring-shaped gate having an inner surface contacting the gate dielectric layer and an outer surface;

a channel region formed to extend in the vertical direction of the active pillar;

a first source/drain region formed at a bottom portion of the active pillar;

a second source/drain region formed at a top portion of the active pillar; and

wherein a width of a widest portion of the outer surface of the ring-shaped gate is equal to or less than that of a widest portion of the outer surface of the ring-shaped insulation spacer.

8. The semiconductor device of claim 7, further comprising a buried bit line formed below the active pillar in the semiconductor substrate and electrically connected to the first source/drain region.

9. The semiconductor device of claim 7, further comprising a word line extending in a horizontal direction and electrically connected to the ring-shaped gate.

10. The semiconductor device of claim 7, further comprising a capacitor electrically connected to the second source/drain region.

11. The semiconductor device of claim 7, further comprising an insulating layer pattern bisecting neighboring first source/drain regions of neighboring unit cells.

12. The device of claim 11, further comprising an ion implantation region below the insulating layer pattern.

13. A method of fabricating a semiconductor device comprising:

forming a plurality of active pillars on a semiconductor substrate to extend in a vertical direction relative to a horizontal primary surface of the semiconductor substrate, the plurality of active pillars formed integrally with the semiconductor substrate;

forming a gate insulating layer covering a surface of the active pillar;

forming a ring-shaped gate surrounding a sidewall of the active pillar on the gate insulating layer in a region of the active pillar;

implanting ions into a region of the semiconductor substrate adjacent to the ring-shaped gate, thereby forming a bottom source/drain region;

covering an outer surface of the ring-shaped gate and the bottom source/drain region with an etch stop layer;

etching the etch stop layer, the bottom source/drain region, and the semiconductor substrate therebelow in a region between two neighboring active pillars of the plurality of active pillars using a photolithography process, thereby defining a buried bit line below the active pillar in the semiconductor substrate; and

forming a word line electrically connected to the ring-shaped gate in a region between two neighboring active pillars of the plurality of active pillars.

14. The method of claim 13, wherein the forming of the buried bit line comprises:

forming a first insulating layer on the bottom source/drain region to completely fill a space between two neighboring active pillars of the plurality of active pillars;

sequentially forming a planarized second insulating layer, a carbon-containing layer, a hard mask layer, and a photoresist pattern on the first insulating layer;

etching the hard mask layer using the photoresist pattern as an etch mask;

etching the carbon-containing layer using the hard mask layer as an etch mask;

etching the planarized second insulating layer and the first insulating layer using the carbon-containing layer as an etch mask, thereby exposing the etch stop layer covering the bottom source/drain region; and

etching the etch stop layer, the bottom source/drain region, and the semiconductor substrate using the planarized second insulating layer as an etch mask, thereby forming a trench line bisecting neighboring first source/drain regions into two isolated regions and thereby defining the buried bit line below the active pillar in the semiconductor substrate.

15. The method of claim 14, wherein the etch stop layer is formed of a nitride layer, and the first insulating layer is formed of an oxide layer.

16. The method of claim 14, wherein the planarized second insulating layer is formed of an oxide layer.

17. The method of claim 14, wherein the carbon-containing layer is formed of an amorphous carbon layer (ACL).

18. The method of claim 14, wherein the hard mask layer is one selected from an oxide layer, an oxynitride layer, and a combination thereof.

19. The method of claim 14, further comprising, after forming the hole defining the buried bit line, performing an ion implantation process into the hole, thereby forming an ion implantation region for isolation in the semiconductor substrate.

20. The method of claim 13, wherein the word line is formed to extend in the direction perpendicular to the buried bit line.

21. The method of claim 20, wherein the forming of the word line comprises:

partially exposing an outer surface of the ring-shaped gate in a region between two neighboring active pillars of the plurality of active pillars; and

depositing a conductive material on the region, thereby forming the word line contacting a surface of the exposed ring-shaped gate.

22. The method of claim 14, wherein the forming of the word line comprises:

filling the inside of the hole with a third insulating layer after forming the hole;

removing a portion of the first insulating layer, a portion of the third insulating layer, and a portion of the etch stop layer in the region between two neighboring active pillars, so as to partially expose an outer surface of the ring-shaped gate; and

depositing a conductive material on the predetermined region, thereby forming the word line contacting an exposed outer surface of the ring-shaped gate.

23. The method of claim 22, wherein the third insulating layer is formed of an oxide layer.

24. The method of claim 13, further comprising:

forming a top source/drain region on an end of the active pillar opposite the semiconductor substrate, so as to form a vertical channel region along the longitudinal direction of the active pillar; and

forming a contact contacting the top source/drain region on the active pillar.

25. The method of claim 24, wherein the contact is a contact connecting the top source/drain region to a lower electrode of a capacitor.

26. The method of claim 24, wherein the forming of the plurality of active pillars comprises:

forming a plurality of mask patterns defining an active pillar region in the semiconductor substrate; and

etching the semiconductor substrate using the mask pattern as an etch mask, thereby forming the active pillar, and wherein forming the contact comprises;

forming a fourth insulating layer concurrently covering a sidewall of the active pillar and a sidewall of the mask pattern in a state that the mask pattern covers an upper surface of the active pillar;

forming a fifth insulating layer having an opening exposing an upper surface of the mask pattern on the fourth insulating layer;

removing the mask pattern exposed through the opening of the fifth insulating layer, so as to expose the upper surface of the active pillar; and

depositing a conductive material on the upper surface of the active pillar to fill an opening of the fifth insulating layer, thereby forming the contact contacting the upper surface of the active pillar.

27. The method of claim 26, wherein the fourth insulating layer and the fifth insulating layer are respectively formed of oxide layers.

28. A method of fabricating a semiconductor device comprising:

providing a cell array region having a plurality of unit cells, each unit cell having a cell occupation area in a semiconductor substrate;

forming an active pillar extending in a vertical direction with respect to the substrate from an active region of each unit cell in the cell array region, the active pillar having a first width portion and a second width portion, the second width portion having a width that is greater than a width of the first width portion;

forming a gate dielectric layer on a sidewall of the active pillar;

forming a ring-shaped insulation spacer on a sidewall of the second width portion of the active pillar, the ring-shaped insulation spacer having an inner surface and an outer surface;

forming a ring-shaped gate on a portion of the gate dielectric layer formed on the sidewall of the active pillar, the ring-shaped gate having an inner surface contacting the gate dielectric layer and an outer surface;

forming a channel region formed to extend in the vertical direction of the active pillar;

forming a first source/drain region formed at a bottom portion of the active pillar;

forming a second source/drain region formed at a top portion of the active pillar; and

wherein a width of a widest portion of the outer surface of the ring-shaped gate is equal to or less than that of a widest portion of the outer surface of the ring-shaped insulation spacer.

29. The method of claim 28, further comprising forming a buried bit line below the active pillar in the semiconductor substrate and electrically connected to the first source/drain region.

30. The method of claim 28, further comprising forming a word line extending in a horizontal direction and electrically connected to the round-shaped gate.

31. The method of claim 28, further comprising forming a capacitor electrically connected to the second source/drain region.

32. The method of claim 28, further comprising forming an insulating layer pattern bisecting the first source/drain regions of neighboring unit cells.

33. The method of claim 29, further comprising forming an ion implantation region below the insulating layer pattern.