Gate technology for strained surface channel and strained buried channel MOSFET devices

• US 20070082470A1
• Filed: 09/13/2006
• Published: 04/12/2007
• Est. Priority Date: 08/07/2000
• Status: Abandoned Application

• Current Assignee: AmberWave Systems Corporation
• Original Assignee: AmberWave Systems Corporation
• Inventors: Hammond, Richard, Fitzgerald, Eugene, Currie, Matthew
• Application Number:
  US11/520,175
• Publication Number:
  US 20070082470A1
• Time in Patent Office: Days
• US Class Current: 438/590
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si_1−xGe_x layer on a substrate, a strained channel layer on the relaxed Si_1−xGe_x layer, and a Si_1−yGe_y layer; removing the Si_1−yGe_y layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

Claims

1-39. -39. (canceled)

40. A method of fabricating a semiconductor device, the method comprising the steps of:

(a) providing a semiconductor heterostructure, the heterostructure comprising a substrate and a strained layer disposed thereover;

(b) providing at least one sacrificial layer disposed over the strained layer;

(c) removing at least a portion of the at least one sacrificial layer, wherein the strained layer remains intact after removal; and

(d) providing a gate dielectric over the strained layer.

41. The method of claim 40 wherein the strained layer comprises a semiconductor material selected from the group consisting of Si, Ge, and SiGe.

42. The method of claim 40 wherein the strained layer has thickness of less than about 300 angstroms.

43. The method of claim 40 wherein the strained layer is substantially free of misfit dislocations.

44. The method of claim 40 wherein the at least one sacrificial layer comprises Si or SiGe.

45. The method of claim 40 wherein step (b) comprises providing a plurality of sacrificial layers disposed over the strained layer, the plurality of sacrificial layers including at least one sacrificial layer comprising Si and at least one sacrificial layer comprising SiGe.

46. The method of claim 40 wherein the substrate comprises Si.

47. The method of claim 46 wherein the semiconductor heterostructure comprises a relaxed Si₁₋

xGe_x layer disposed between the substrate and the strained layer.

48. The method of claim 47 wherein the semiconductor heterostructure comprises a buffer layer disposed between the substrate and relaxed Si₁₋

xGe_x layer.

49. The method of claim 46 wherein the semiconductor heterostructure comprises an insulator layer disposed over the substrate, the strained layer being disposed over the insulator layer.

50. The method of claim 40 wherein at least a portion of the at least one sacrificial layer is removed using a technique selected from the group consisting of:

wet oxidation, dry oxidation, wet etching, and dry etching.

51. The method of claim 50 wherein at least a portion of the at least one sacrificial layer is removed using the wet oxidation technique at a temperature up to about 750°

C.

52. The method of claim 40 wherein step (d) comprises oxidizing at least a portion of the strained layer thereby providing the gate dielectric thereon.

53. The method of claim 40 wherein step (d) comprises depositing a dielectric layer over at least portion of the strained layer thereby providing the gate dielectric.

54. A method of fabricating a semiconductor device, the method comprising the steps of:

(a) providing a semiconductor heterostructure, the heterostructure comprising a substrate and a strained layer having first thickness disposed thereover;

(b) providing at least one sacrificial layer disposed over the strained layer;

(c) removing the at least one sacrificial layer and a portion of the strained layer, the portion having second thickness substantially less than the first thickness; and

(d) providing a gate dielectric over the strained layer.

55. The method of claim 54 wherein the strained layer comprises a semiconductor material selected from the group consisting of Si, Ge, or SiGe.

56. The method of claim 54 wherein the first thickness is less than about 300 angstroms.

57. The method of claim 54 wherein the substrate comprises Si.

58. The method of claim 57 wherein the semiconductor heterostructure comprises a relaxed Si₁₋

xGe_x layer disposed between the substrate and the strained layer.

59. The method of claim 58 wherein the semiconductor heterostructure comprises a buffer layer disposed between the substrate and relaxed Si₁₋

xGe_x layer.

60. The method of claim 57 wherein the semiconductor heterostructure comprises an insulator layer disposed over the substrate, the strained layer being disposed over the insulator layer.

61. The method of claim 54 wherein at least one the at least one sacrificial layer and a portion of the strained layer are removed using a technique selected from the group consisting of:

wet oxidation, dry oxidation, wet etching, and dry etching.

62. The method of claim 54 wherein at least one the at least one sacrificial layer and a portion of the strained layer are using the wet oxidation technique at a temperature up to about 750°

C.

63. The method of claim 54 wherein step (d) comprises oxidizing at least a portion of the strained layer thereby providing the gate dielectric thereon.

64. The method of claim 54 wherein step (d) comprises depositing a dielectric layer over at least portion of the strained layer thereby providing the gate dielectric.

65. The method of claim 54 wherein the strained layer is substantially free of misfit dislocations.

66. The method of claim 54 wherein the second first thickness is less than about 10 angstroms.