ULTRA THIN FET

• US 20070082480A1
• Filed: 09/08/2006
• Published: 04/12/2007
• Est. Priority Date: 09/08/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Briere, Michael, Lidow, Alexander, Kinzer, Daniel
• Granted Patent: US 7,955,969 B2
• Time in Patent Office: Days
• US Class Current: 438/629
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts while the wafer bulk is intact. The top surface is then contacted by a rigid wafer carrier and the bulk wafer is then ground/etched to an etch stop layer at the bottom of the thin wafer. A thick bottom contact is then applied to the bottom surface and the top wafer carrier is removed. All three contacts of a MOSFET may be formed on the top surface in one embodiment or defined by the patterning of the bottom metal contact.

Claims

1. The process of manufacture of a semiconductor device having a die thickness less than about 10 micrometers;

said process comprising forming an etch stop layer in the top surface of a wafer having a thickness greater than about 300 micrometers;

forming a thin junction receiving layer of semiconductor material of thickness less than about 10 microns atop said etch stop layer;

forming a junction pattern in said thin junction receiving layer and forming spaced coplanar contacts atop said thin junction receiving layer;

removably attaching a wafer carrier mount to said top surface of said thin junction receiving layer;

removing the bulk of said wafer from its bottom surface to said etch stop layer with said wafer carrier providing sufficient strength to said thin layer to permit its handling without breakage;

metallizing the exposed bottom surface of said wafer with a conductive layer of sufficient thickness and strength to allow handling of said thin layer without damage; and

thereafter removing said removable wafer carrier mount.

2. The process of claim 1, wherein said thin junction receiving layer includes a layer of epitaxially deposited silicon.

3. The process of claim 1, wherein said wafer is N type monocrystalline silicon, and wherein said thin junction receiving layer comprises a thin N⁺ drift region and an N⁻

epitaxially deposited layer atop said N⁺ drift region.

4. The process of claim 1, wherein said step of removing said bulk of said wafer includes a grind step and final etch step to said etch stop layer.

5. The process of claim 2, wherein said step of removing said bulk of said wafer includes a grind step and final etch step to said etch stop layer.

6. The process of claim 3, wherein said step of removing said bulk of said wafer includes a grind step and final etch step to said etch stop layer.

7. The process of claim 1, wherein said conductive layer is copper and has a thickness greater than about 10 micrometers.

8. The process of claim 2, wherein said conductive layer is copper and has a thickness greater than about 10 micrometers.

9. The process of claim 3, wherein said conductive layer is copper and has a thickness greater than about 10 micrometers.

10. The process of claim 4, wherein said conductive layer is copper and has a thickness greater than about 10 micrometers.

11. The process of claim 6, wherein said conductive layer is copper and has a thickness greater than about 10 micrometers.

12. The process of claim 1, which further includes the step of forming a via through said thin junction receiving layer and filling said via with a conductive material to connect at least one of said contacts on the top surface of said thin junction receiving layer to said conductive layer on said exposed bottom surface of said wafer.

13. The process of claim 3, which further includes the step of forming a via through said thin junction receiving layer and filling said via with a conductive material to connect at least one of said contacts on the top surface of said thin junction receiving layer to said conductive layer on said exposed bottom surface of said wafer.

14. The process of claim 4, which further includes the step of forming a via through said thin junction receiving layer and filling said via with a conductive material to connect at least one of said contacts on the top surface of said thin junction receiving layer to said conductive layer on said exposed bottom surface of said wafer.

15. The process of claim 7, which further includes the step of forming a via through said thin junction receiving layer and filling said via with a conductive material to connect at least one of said contacts on the top surface of said thin junction receiving layer to said conductive layer on said exposed bottom surface of said wafer.

16. The process of claim 1, which includes the further step of forming street openings between die positions in said thin junction receiving layer, and filling said street openings with conductive material to connect at least one of said contacts on the top surface of said thin junction receiving layer to said conductive layer on said exposed bottom surface of said layer, and opening a window in said conductive layer to isolate a portion thereof from said material connected to said top surface contact, whereby at least two contacts for each die are connectable at the bottom surface of said die.

17. The process of claim 3, which includes the further step of forming street openings between die positions in said thin junction receiving layer, and filling said street openings with conductive material to connect at least one of said contacts on the top surface of said thin junction receiving layer to said conductive layer on said exposed bottom surface of said layer, and opening a window in said conductive layer to isolate a portion thereof from said material connected to said top surface contact, whereby at least two contacts for each die are connectable at the bottom surface of said die.

18. The process of claim 4, which includes the further step of forming street openings between die positions in said thin junction receiving layer, and filling said street openings with conductive material to connect at least one of said contacts on the top surface of said thin junction receiving layer to said conductive layer on said exposed bottom surface of said layer, and opening a window in said conductive layer to isolate a portion thereof from said material connected to said top surface contact, whereby at least two contacts for each die are connectable at the bottom surface of said die.

19. The process of claim 7, which includes the further step of forming street openings between die positions in said thin junction receiving layer, and filling said street openings with conductive material to connect at least one of said contacts on the top surface of said thin junction receiving layer to said conductive layer on said exposed bottom surface of said layer, and opening a window in said conductive layer to isolate a portion thereof from said material connected to said top surface contact, whereby at least two contacts for each die are connectable at the bottom surface of said die.