Flash memory management

• US 20070083697A1
• Filed: 10/07/2005
• Published: 04/12/2007
• Est. Priority Date: 10/07/2005
• Status: Abandoned Application

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Isard, Michael, Wobber, Edward, Birrell, Andrew, Thacker, Charles
• Application Number:
  US11/245,919
• Publication Number:
  US 20070083697A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

Flash memory is managed utilizing memory management data structures residing in volatile memory of a flash memory device. The memory management data structures are created and updated each time power is supplied to the memory device. During write operations to the flash memory, specific locations in the flash memory are updated to reflect the current status of the flash memory. When power is interrupted, the memory management data structures are recreated upon reapplication of power. The flash memory is scanned and the information obtained from the specific locations in the flash memory is utilized to construct the memory management data structures. No bad block tables are required. Flash memory is managed to provide relatively good random write performance and to accommodate power interruptions. Applications include the use of flash memory for general purpose computing and devices in which power can fail at any time (due to being unplugged for example).

Claims

1. A method for managing memory, said method comprising:

accessing memory in accordance with a memory management data structure, said memory management data structure comprising information pertaining to said memory;

dynamically updating designated locations of said memory with information pertaining to memory status; and

dynamically updating said memory management data structure with information pertaining to memory status.

2. A method in accordance with claim 1, further comprising:

creating said memory management data structure in accordance with said information stored in said designated locations in said memory.

3. A method in accordance with claim 2, wherein:

said memory comprises flash memory;

said memory management data structure is stored in volatile memory; and

said memory management data structure is constructed each time power is applied to said volatile memory subsequent a lack of power to said volatile memory.

4. A method in accordance with claim 1, said memory comprising a plurality of blocks, each block comprising a plurality of pages, wherein said designated locations in said memory comprise:

a first designated page in each block, each first designated page of each respective block being indicative of;

a status of a respective block being one of good and bad; and

a respective block being one of erased and not erased; and

a second designated page in each block, each second designated page of each respective block being indicative of;

a relationship between a logical block address and each page of a respective block;

a validity status of portions of each page of a respective block; and

a block sequence number indicative of a number of times blocks in said memory have been erased.

5. A method in accordance with claim 4, further comprising constructing said memory management data structure, said act of constructing comprising:

reading each first designated page in each block;

constructing said memory management data structure in accordance with information contained in each read first designated page;

reading each second designated page in each block; and

constructing said memory management data structure in accordance with information contained in each read second designated page.

6. A method in accordance with claim 5, wherein:

said second designated page is read prior to attempting to read said second designated page; and

said first designated page is read only if an error occurs in reading said second designated page.

7. A method in accordance with claim 5, wherein said memory management data structure is reconstructed each time power is applied to said memory subsequent a lack of power to said memory.

8. A method in accordance with claim 5, said memory management data structure being indicative of an active page of said memory, wherein an active page is indicative of a next page to be written in response to a write command.

9. A method in accordance with claim 8, further comprising:

upon writing to said active page, updating said memory management data structure to be indicative of a location of a next active page, wherein said next active page comprises an erased page having a lowest page address in one of;

a block currently being accessed; and

if said block currently being access is full, a next available block.

10. A method in accordance with claim 1, said memory comprising a plurality of blocks and each block comprising a plurality of pages, wherein said memory management data structure comprises at least one of:

a data structure indicative of a relationship between logical block addresses and page addresses of said memory and a validity status of portions of each page of a respective block;

a data structure indicative of erased blocks available for writing;

a data structure indicative of a number of valid pages in each block;

a data structure indicative of a next page to be written in response to a write command; and

a data structure indicative of a block sequence number indicative of a number of times blocks in said memory have been erased.

11. An apparatus for managing memory, said apparatus comprising:

a first memory portion for comprising a memory management data structure for managing a second memory portion;

said second memory portion comprising a plurality of blocks, each block comprising a plurality of pages; and

a controller portion for;

controlling access to said second memory portion; and

constructing said memory management data structure.

12. An apparatus in accordance with claim 11, wherein:

said first memory portion comprises volatile memory; and

said second memory portion comprises non-volatile memory.

13. An apparatus in accordance with claim 11, wherein said second memory portion comprises flash memory.

14. An apparatus in accordance with claim 11, wherein said second memory portion comprises:

a first designated page in each block, each first designated page of each respective block being indicative of;

a status of a respective block being one of good and bad; and

a respective block being one of erased and not erased; and

a second designated page in each block, each second designated page of each respective block being indicative of;

a association between a logical block address and each page of a respective block;

a validity status of portions of each page of a respective block; and

a block sequence number indicative of a number of times a blocks in said memory have been erased.

15. An apparatus in accordance with claim 14, wherein said controller portion constructs said memory management data structure in said first memory portion in accordance with information contained in said first and second designated pages each time power is applied to said first memory portion subsequent a lack of power to said first memory portion.

16. An apparatus in accordance with claim 11, wherein said memory management data structure comprises at least one of:

a data structure indicative of a relationship between logical block addresses and page addresses of said second memory portion and a validity status of portions of each page of a respective block;

a data structure indicative of erased blocks available for writing;

a data structure indicative of a number of valid pages in each block;

a data structure indicative of a next page to be written in response to a write command; and

a data structure indicative of a block sequence number indicative of a number of times blocks in said memory have been erased.

17. A computer-readable medium having computer-executable instructions for performing the acts of:

creating a memory management data structure in a first memory in accordance with information stored in designated locations in a second memory, wherein said memory management data structure is created each time power is applied to said first memory subsequent a lack of power to said first memory;

accessing said second memory in accordance with said memory management data structure, said memory management data structure comprising information pertaining to said second memory;

dynamically updating designated locations of said second memory with information pertaining to second memory status; and

dynamically updating said memory management data structure with information pertaining to second memory status.

18. A computer-readable medium in accordance with claim 17, wherein said second memory comprises a plurality of blocks and each block comprises a plurality of pages, said computer-readable medium having further computer-executable instructions for:

reading a first designated page in each respective block, wherein a first designated page of each respective block is indicative of;

a status of a respective block being one of good and bad; and

a respective block being one of erased and not erased;

constructing said memory management data structure in accordance with information contained in each read first designated page;

reading a second designated page in each respective block, wherein a second designated page of each respective block is indicative of;

a relationship between a logical block address and each page of a respective block;

a validity status of portions of each page of a respective block; and

a block sequence number indicative of a number of times blocks in said memory have been erased; and

constructing said memory management data structure in accordance with information contained in each read second designated page.

19. A computer-readable medium in accordance with claim 17, wherein said memory management data structure is indicative of an active page of said second memory, said active page being indicative of a next page to be written in response to a write command, said computer-readable medium having further computer-executable instructions for:

upon writing to said active page, updating said memory management data structure to be indicative of a location of a next active page, wherein said next active page comprises an erased page having a lowest page address in one of;

a block currently being accessed; and

if said block currently being accessed is full, a next available block.

20. A computer-readable medium in accordance with claim 17, said second memory comprising a plurality of blocks and each block comprising a plurality of pages, wherein said memory management data structure comprises at least one of:

a data structure indicative of a relationship between logical block addresses and page addresses of said second memory and a validity status of portions of each page of a respective block;

a data structure indicative of erased blocks available for writing;

a data structure indicative of a number of valid pages in each block;

a data structure indicative of a next page to be written in response to a write command; and

a data structure indicative of a block sequence number indicative of a number of times blocks in said memory have been erased.