Power throttling in a memory system

• US 20070083701A1
• Filed: 10/12/2005
• Published: 04/12/2007
• Est. Priority Date: 10/12/2005
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Kapil, Sanjiv
• Granted Patent: US 7,496,777 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system is disclosed. The memory system includes a memory controller coupled to one or more memory modules, at least one of the memory modules including a buffer. The memory controller is configured to convey a command to at least one of the memory modules in response to detecting that no memory requests addressed to the at least one of the memory modules have been received during a specified window of time. In response to the command, the buffer of the at least one of the memory modules is configured to enter a reduced power state. The specified window of time may be either a specified number of memory refresh intervals or buffer sync intervals. The memory controller maintains a count of memory refresh or buffer sync intervals.

Claims

1. A memory system comprising:

a memory controller coupled to one or more memory modules, at least one of the memory modules including a buffer;

wherein the memory controller is configured to convey a command to at least one of the memory modules in response to detecting that no memory requests addressed to the at least one of the memory modules have been received during a specified window of time; and

wherein in response to the command, the buffer of the at least one of the memory modules is configured to enter a reduced power state.

2. The system of claim 1,

wherein the specified window of time comprises a specified number of refresh intervals;

and

wherein the memory controller is further configured to;

maintain a count of memory refresh intervals; and

each time the count reaches the specified number, determine whether or not any memory requests addressed to the at least one of the memory modules have been received during an immediately preceding window of time equal in duration to the specified window of time.

3. The system of claim 2, wherein the memory controller is further configured to restart said count in response to detecting that either a memory request addressed to the at least one of the memory modules has been received, or the count has reached the specified number.

4. The system of claim 1,

wherein the specified window of time comprises a specified number of buffer sync intervals;

and

wherein to the memory controller is configured to;

maintain a count of buffer sync intervals; and

each time the count reaches the specified number;

restart the count of buffer sync intervals; and

determine whether or not any memory requests addressed to the at least one of the memory modules have been received during an immediately preceding window of time equal in duration to the specified window of time.

5. The system of claim 4, wherein the memory controller is further configured to restart said count in response to detecting that a memory request addressed to the at least one of the memory modules has been received.

6. The system of claim 1,

wherein the memory controller is further configured to:

monitor one or more windows of time, each window corresponding to a respective memory module; and

convey a command to each memory module for which no memory requests have been received during the corresponding window of time, which causes the corresponding buffer to enter a reduced power state.

7. A method of reducing power consumption in a memory subsystem, the method comprising:

conveying a command to at least one of one or more memory modules in response to detecting that no memory requests addressed to the at least one of the memory modules have been received during a specified window of time, wherein at least one of the memory modules comprises a buffer coupled to one or more memory devices; and

in response to the command, placing at least one buffer of the at least one of the memory modules into a reduced power state.

8. The method of claim 7, wherein the specified window of time comprises a specified number of refresh intervals, the method further comprising:

maintaining a count of memory refresh intervals;

each time the count reaches a specified number, determining whether or not any memory requests addressed to the at least one of the memory modules have been received during an immediately preceding window of time equal in duration to the specified window of time.

9. The method of claim 8, further comprising restarting the count in response to detecting that either a memory request addressed to the at least one of the memory modules has been received, or the count has reached the specified number.

10. The method of claim 7, wherein the specified window of time comprises a specified number of buffer sync intervals, the method further comprising:

maintaining a count of buffer sync intervals;

each time the count reaches a specified number, determining whether or not any memory requests addressed to the at least one of the memory modules have been received during an immediately preceding window of time equal in duration to the specified window of time.

11. The method of claim 10, further comprising restarting the count in response to detecting that either a memory request addressed to the at least one of the memory modules has been received, or the count has reached the specified number.

12. The method of claim 7, further comprising:

monitoring one or more windows of time, each window corresponding to a respective memory module; and

conveying a command to each memory module for which no memory requests have been received during the corresponding window of time, which causes the corresponding buffer to enter a reduced power state.

13. A processor comprising:

a memory controller configured to be coupled to one or more memory modules, at least one of the memory modules including a buffer;

wherein the processor is configured to generate and convey memory requests to the memory controller;

wherein the memory controller is configured to convey a command to at least one of the memory modules in response to detecting that no memory requests addressed to the at least one of the memory modules have been received by the memory controller during a specified window of time; and

wherein in response to the command, at least one buffer of the at least one of the memory modules is configured to enter a reduced power state.

14. The processor of claim 13,

wherein the specified window of time comprises a specified number of refresh intervals;

and

wherein the memory controller is further configured to;

monitor the status of a memory request queue;

maintain a count of memory refresh intervals; and

each time the count reaches the specified number, determine whether or not any memory requests addressed to the at least one of the memory modules have entered the memory request queue during an immediately preceding window of time equal in duration to the specified window of time.

15. The processor of claim 14, wherein the memory controller is further configured to restart the running count of memory refresh intervals in response to detecting that either a memory request has entered the memory request queue, or the count has reached the specified number.

16. The processor of claim 13,

wherein the specified window of time comprises a specified number of buffer sync intervals;

and

wherein to the memory controller is configured to;

monitor the status of a memory request queue;

maintain a count of buffer sync intervals; and

each time the count reaches the specified number, determine whether or not any memory requests addressed to the at least one of the memory modules have entered the memory request queue during an immediately preceding window of time equal in duration to the specified window of time.

17. The processor of claim 16, wherein the memory controller is further configured to restart the running count of buffer sync intervals in response to detecting that either a memory request has entered the memory request queue, or the count has reached the specified number.

18. The processor of claim 13,

wherein the memory controller is further configured to:

monitor one or more windows of time, each window corresponding to a respective memory module; and

convey a command to each memory module for which no memory requests have been received during the corresponding window of time, which causes the corresponding buffer to enter a reduced power state.

19. A memory controller comprising:

a memory request queue configured to store received memory requests; and

circuitry configured to;

convey a command in response to detecting that no memory requests addressed to a particular memory module has been received by the memory controller during a specified window of time; and

wherein the command is configured to cause a buffer of a memory module to which it is addressed to enter a reduced power state.

20. The memory controller of claim 19, wherein the specified window of time comprises a specified number of refresh intervals, and wherein the circuitry is further configured to:

monitor the status of the memory request queue;

maintain a count of memory refresh intervals; and

each time the count reaches the specified number, determine whether or not any memory requests addressed to the particular memory module have entered the memory request queue during an immediately preceding window of time equal in duration to the specified window of time.

21. The memory controller of claim 20, wherein the memory controller is further configured to restart the count of memory refresh intervals in response to detecting that either a memory request addressed to the particular memory module has entered the memory request queue, or the count has reached the specified number.

22. The memory controller of claim 19,

wherein the specified window of time comprises a specified number of buffer sync intervals;

and

wherein to the memory controller is configured to;

monitor the status of a memory request queue;

maintain a count of buffer sync intervals; and

each time the count reaches the specified number, determine whether or not any memory requests addressed to the particular memory module have entered the memory request queue during an immediately preceding window of time equal in duration to the specified window of time.

23. The memory controller of claim 22, wherein the memory controller is further configured to restart the count of buffer sync intervals in response to detecting that either a memory request has entered the memory request queue, or the count has reached the specified number.

24. The memory controller of claim 19,

wherein the memory controller is further configured to:

monitor one or more windows of time, each window corresponding to a respective memory module; and

convey a command to each memory module for which no memory requests have been received during the corresponding window of time, which causes the corresponding buffer to enter a reduced power state.