System with high power and low power processors and thread transfer

• US 20070083785A1
• Filed: 09/20/2006
• Published: 04/12/2007
• Est. Priority Date: 06/10/2004
• Status: Abandoned Application

• Current Assignee: Electronics and Telecommunications Research Institute, Marvell World Trade Limited (Marvell Technology Group Limited), The Industry & Academic Cooperation In Chungnam National University
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat
• Application Number:
  US11/523,996
• Publication Number:
  US 20070083785A1
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system on chip (SOC) includes first and second processors and a control module. The first processor implemented by the SOC has active and inactive states and processes first and second sets of threads during the active state. The second processor implemented by the SOC has active and inactive states, wherein the second processor consumes less power when operating in the active state than the first processor operating in the active state. The control module, implemented by the SOC communicates with the first and second processors, selectively transfers the second set of threads from the first processor to the second processor and selects the inactive state of the first processor. The second processor processes the second set of threads.

Claims

1. A system on chip (SOC) comprising:

a first processor implemented by said SOC that has active and inactive states and that processes first and second sets of threads during said active state;

a second processor implemented by said SOC that has active and inactive states, wherein said second processor consumes less power when operating in said active state than said first processor operating in said active state; and

a control module implemented by said SOC that communicates with said first and second processors and that selectively transfers said second set of threads from said first processor to said second processor and selects said inactive state of said first processor, wherein said second processor processes said second set of threads.

2. The SOC of claim 1 further comprising a register file implemented by said SOC that communicates with said first processor and said second processor and that stores thread information for said first and second processors.

3. The SOC of claim 2 wherein said thread information includes at least one of registers, checkpoints, and program counters for said threads of said first and second processors.

4. The SOC of claim 1 further comprising:

a first register file that communicates with said first processor and that stores first thread information for said first processor; and

a second register file that communicates with said second processor and that stores second thread information for said second processor.

5. The SOC of claim 4 wherein said first and second thread information includes at least one of registers, checkpoints, and program counters for said threads of said first and second processors, respectively.

6. The SOC of claim 4 wherein said control module transfers said thread information from said first register file to said second register file when transferring said threads from said first processor to said second processor.

7. The SOC of claim 1 wherein said first processor includes first transistors and said second processor includes second transistors, and wherein said first transistors have a higher leakage current than said second transistors.

8. The SOC of claim 1 wherein said first processor includes first transistors and said second processor includes second transistors, and wherein said second transistors have a greater size than said first transistors.

9. The SOC of claim 1 wherein said SOC is in a high-power mode when said first processor is in an active state and a low-power mode when said first processor is in an inactive state.

10. The SOC of claim 1 wherein said first and second processors comprise first and second graphics processing units, respectively.

31. The SOC of claim 1 wherein said first processor has a higher number of stages than said second processor.

32. The SOC of claim 1 wherein said first processor has a higher number of parallel pipelines than said second processor.

11. A method for processing data, comprising:

implementing first and second processors on a system on chip (SOC), wherein said first and second processors have active and inactive states, and wherein said second processor consumes less power when operating in said active state than said first processor operating in said active state;

processing first and second sets of threads during said active state using said first processor;

selectively transferring said second set of threads from said first processor to said second processor and selecting said inactive state of said first processor; and

processing said second set of threads using said second processor.

12. The method of claim 11 further comprising:

implementing a register file using said SOC; and

storing thread information for said first and second processors in said register file.

13. The method of claim 12 wherein said thread information includes at least one of registers, checkpoints, and program counters for said threads of said first and second processors.

14. The method of claim 11 further comprising:

implementing a first register file using said SOC;

storing first thread information for said first processor in said first register file;

implementing a second register file using said SOC; and

storing second thread information for said second processor.

15. The method of claim 14 wherein said first and second thread information includes at least one of registers, checkpoints, and program counters for said threads of said first and second processors, respectively.

16. The method of claim 14 further comprising transferring said thread information from said first register file to said second register file when transferring said threads from said first processor to said second processor.

17. The method of claim 11 wherein said first processor includes first transistors and said second processor includes second transistors, and wherein said first transistors have a higher leakage current than said second transistors.

18. The method of claim 11 wherein said first processor includes first transistors and said second processor includes second transistors, and wherein said second transistors have a greater size than said first transistors.

19. The method of claim 11 further comprising operating in a high-power mode when said first processor is in an active state and in a low-power mode when said first processor is in an inactive state.

20. The method of claim 11 wherein said first and second processors comprise first and second graphics processing units, respectively.

33. The method of claim 11 wherein said first processor has a higher number of stages than said second processor.

34. The method of claim 11 wherein said first processor has a higher number of parallel pipelines than said second processor.

21. A system on chip (SOC) comprising:

first processing means, implemented by said SOC that has active and inactive states, for processing first and second sets of threads during said active state;

second processing means for processing, that is implemented by said SOC and that has active and inactive states, wherein said second processing means consumes less power when operating in said active state than said first processing means operating in said active state; and

control means, implemented by said SOC, for communicating with said first and second processing means, for selectively transferring said second set of threads from said first processing means to said second processing means and selecting said inactive state of said first processing means, wherein said second processing means processes said second set of threads.

22. The SOC of claim 21 further comprising register means, implemented by said SOC and that communicates with said first processing means and said second processing means, for storing thread information for said first and second processing means.

23. The SOC of claim 22 wherein said thread information includes at least one of registers, checkpoints and program counters for said threads of said first and second processing means.

24. The SOC of claim 21 further comprising:

first register means that communicates with said first processing means for storing first thread information for said first processing means; and

second register means that communicates with said second processing means for storing second thread information for said second processing means.

25. The SOC of claim 24 wherein said first and second thread information includes at least one of registers, checkpoints and program counters for said threads of said first and second processing means, respectively.

26. The SOC of claim 24 wherein said control means transfers said thread information from said first register means to said second register means when transferring said threads from said first processing means to said second processing means.

27. The SOC of claim 21 wherein said first processing means includes first transistors and said second processing means includes second transistors, and wherein said first transistors have a higher leakage current than said second transistors.

28. The SOC of claim 21 wherein said first processing means includes first transistors and said second processing means includes second transistors, and wherein said second transistors have a greater size than said first transistors.

29. The SOC of claim 21 wherein said SOC is in a high-power mode when said first processing means is in an active state and a low-power mode when said first processing means is in an inactive state.

30. The SOC of claim 21 wherein said first and second processing means comprise first and second graphics processing means for processing graphics, respectively.

35. The SOC of claim 21 wherein said first processing means has a higher number of stages than said second processing means.

36. The SOC of claim 21 wherein said first processing means has a higher number of parallel pipelines than said second processing means.