Methods and apparatus for task sharing among a plurality of processors

• US 20070083870A1
• Filed: 07/29/2005
• Published: 04/12/2007
• Est. Priority Date: 07/29/2005
• Status: Abandoned Application

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Kanakogi, Tomochika
• Application Number:
  US11/193,708
• Publication Number:
  US 20070083870A1
• Time in Patent Office: Days
• US Class Current: 718/105
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3888 controlled by a single instruction for multiple threads [SIMT] in parallel
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

A method is disclosed which may include issuing a plurality of instructions in a processing pipeline of a first processor within a multiprocessor system; determining whether a second processor in the multiprocessor system is in at least one of a running state and a waiting state; and transferring at least one of the instructions to execution stages of a processing pipeline of the second processor and bypassing at least one earlier stage of the processing pipeline of the second processor, when the second processor is in the waiting state.

Claims

1. A method, comprising:

issuing a plurality of instructions in a processing pipeline of a first processor within a multiprocessor system;

determining whether a second processor in said multiprocessor system is in at least one of a running state and a waiting state; and

transferring at least one of said instructions to execution stages of a processing pipeline of said second processor and bypassing at least one earlier stage of said processing pipeline of said second processor, when said second processor is in said waiting state.

2. The method of claim 1 wherein said bypassing comprises bypassing at least one of a fetch stage, a decode stage, and an issue stage of said processing pipeline of said second processor.

3. The method of claim 2 further comprising:

selecting, within said processing pipeline of said second processor, between receiving instructions issued from said first processor or receiving instructions issued from said processing pipeline of said second processor.

4. The method of claim 1 further comprising:

generating execution stage results by executing said transferred instructions in said second processor.

5. The method of claim 4 further comprising:

returning said execution stage results to said first processor.

6. The method of claim 4 further comprising:

receiving said execution stage results into said register file of said processing pipeline of said first processor.

7. The method of claim 1 wherein said transferring comprises:

transferring said instructions only if said first processor is in a running state.

8. The method of claim 1 further comprising:

executing instructions in said first processor concurrently with executing said transferred instructions in said second processor.

9. The method of claim 8 further comprising reducing an operating frequency of at least a portion of said first processor and of at least a portion of said second processor during said concurrent execution.

10. The method of claim 9 wherein said reducing comprises reducing said operating frequency of said first and second processors by about 50% during said concurrent execution.

11. The method of claim 9 wherein at least one of:

said portion of said first processor includes a register file and execution stages of said processing pipeline of said first processor; and

said portion of said second processor includes said execution stages of said processing pipeline of said second processor.

12. The method of claim 1 further comprising:

transitioning from said running state to said waiting state in a given one of said processors when no instructions remain in said pipeline of said given processor.

13. The method of claim 11 further comprising:

transitioning from said waiting state to said running state in a given one of said first and second processors when at least one of;

a) at least one instruction arrives within a pipeline of said given processor; and

b) at least one instruction is transferred to said given processor from the other processor.

14. The method of claim 1 further comprising initiating said determining and said transferring by a processor unit (PU) of said multiprocessor system.

15. A multiprocessor system, comprising:

a first processor including a pipeline having at least an instruction issue stage for issuing a plurality of instructions;

a second processor including a pipeline having at least an execution stage and at least one earlier stage;

a first communication link coupled between said first and second processors such that at least one of said instructions may bypass said at least one earlier stage for execution in said execution stage of said second processor when said second processor is in a waiting state.

16. The multiprocessor system of claim 15 further comprising:

a second communication link coupled between said first and second processors such that execution stage results generated in said second processor may bypass a later stage of said pipeline of said second processor when said second processor is in said waiting state.

17. The multiprocessor system of claim 15 wherein said first communication link enables said at least one instruction to bypass at least one of a fetch stage, a decode stage, and an issue stage of said processing pipeline of said second processor.

18. The multiprocessor system of claim 15 wherein said multiprocessor system is operable to select, within said processing pipeline of said second processor, between receiving instructions issued from said first processor or receiving instructions issued from said processing pipeline of said second processor.

19. The multiprocessor system of claim. 15 wherein said multiprocessor system is operable to generate execution stage results in said second processor by executing said at least one instruction.

20. The multiprocessor system of claim 19 wherein said multiprocessor system is operable to return said execution stage results to said first processor.

21. The multiprocessor system of claim 20 wherein said multiprocessor system is operable to receive said execution stage results into a register file of said processing pipeline of said first processor.

22. The multiprocessor system of claim 15 wherein said multiprocessor system is operable to enable said at least one instruction to bypass said earlier stage of said pipeline of said second processor only when said first processor is in a running state.

23. The multiprocessor of claim 15 wherein said multiprocessor system is operable to execute instructions in said first processor concurrently with said execution in said second processor of said at least one instruction.

24. The multiprocessor of claim 23 wherein said multiprocessor system is operable to reduce an operating frequency of at least a portion of said first processor and of at least a portion of said second processor during said concurrent execution.

25. The multiprocessor system of claim 24 wherein said reducing comprises reducing said operating frequency of said first and second processors by about 50% during said concurrent execution.

26. The multiprocessor system of claim 24 wherein at least one of:

said portion of said first processor includes a register file and execution stages of said processing pipeline of said first processor; and

said portion of said second processor includes said execution stage of said processing pipeline of said second processor.

27. The multiprocessor system of claim 15 wherein said first communication link between said first and second processors is established during a manufacture of said multiprocessor system.

28. The multiprocessor system of claim 15 wherein said first communication link extends from said instruction issue stage of said first processor to said execution stage of said second processor.

29. The multiprocessor system of claim 16 wherein said second communication link extends from said execution stage of said second processor to a register file of said first processor.

30. The multiprocessor system of claim 16 further comprising:

an instruction selection multiplexer, in said second processor, disposed between said first communication link and said execution stage.

31. The multiprocessor system of claim 30 wherein said instruction selection multiplexer is operable to select between instructions issued from said second processor and instructions transferred along said first communication link.

32. The multiprocessor system of claim 15 wherein said execution stage of said second processor comprises an instruction buffer and at least one execution unit.

33. The multiprocessor system of claim 16 further comprising:

an execution results multiplexer, in said first processor, disposed between second communication link and a register file of said first processor.

34. The multiprocessor system of claim 33 wherein said execution results multiplexer is operable to select between execution stage results generated in said first processor and said execution stage results generated in said second processor.