Liquid crystal display device and method of fabricating the same

• US 20070085079A1
• Filed: 06/20/2006
• Published: 04/19/2007
• Est. Priority Date: 10/18/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Nam, Sung-Lim, Lee, Na-Kyung
• Granted Patent: US 7,732,814 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A liquid crystal display (LCD) device includes a gate line and a data line crossing each other to define a pixel region on a first substrate, a thin film transistor connected to the gate line and the data line, a first protrusion and a second protrusion formed on the first substrate, a pixel electrode connected to the thin film transistor in the pixel region, a first patterned spacer and a second patterned spacer formed on a second substrate facing the first substrate, wherein the first patterned spacer corresponds to the first protrusion, and the second patterned spacer corresponds to the second protrusion.

Claims

1. A liquid crystal display (LCD) device, comprising:

a first substrate and a second substrate facing each other and having a liquid crystal layer interposed therebetween;

a gate line and a data line crossing each other to define a pixel region on the first substrate;

a thin film transistor connected to the gate and data lines;

a first protrusion and a second protrusion formed on the first substrate;

a pixel electrode connected to the thin film transistor in the pixel region; and

a first patterned spacer and a second patterned spacer formed on the second substrate, wherein the first patterned spacer corresponds to the first protrusion and the second patterned spacer corresponds to the second protrusion.

2. The LCD device according to claim 1, wherein the first protrusion has a first height and the second protrusion has a second height such that the first height is greater than the second height.

3. The LCD device according to claim 2, wherein the first patterned spacer and the second patterned spacer have substantially a same height, such that the first patterned spacer contacts the first protrusion and the second patterned spacer is separated from the second protrusion.

4. The LCD device according to claim 3, wherein the second patterned spacer is separated from the second protrusion by a gap less than about 0.3 μ

m.

5. The LCD device according to claim 1, wherein the first protrusion includes a triple-layered structure, and the second protrusion includes a single-layered structure.

6. The LCD device according to claim 1, wherein the gate line has a first portion with a first width corresponding to the first and second protrusions and a second portion with a second width, the first width being greater than the second width.

7. The LCD device according to claim 1, wherein the thin film transistor includes a gate electrode extending from the gate line, a gate insulating layer on the gate electrode, a semiconductor layer including an active layer and an ohmic contact layer on the gate insulating layer, and source and drain electrodes spaced apart from each other on the semiconductor layer.

8. The LCD device according to claim 7, wherein the first protrusion includes a first layer, a second layer and a third layer such that the first layer is formed of a same layer as the active layer, the second layer is formed of a same layer as the ohmic contact layer, and the third layer is formed of a same layer as the source and drain electrodes.

9. The LCD device according to claim 7, wherein the second protrusion is formed of a same layer as the active layer.

10. The LCD device according to claim 1, wherein the first and second protrusions are arranged over the gate line.

11. The LCD device according to claim 1, further comprising a black matrix formed between the second substrate and the first patterned spacer and between the second substrate and the second patterned spacer, the black matrix corresponding to the gate and data lines.

12. The LCD device according to claim 11, further comprising a color filter layer formed between the black matrix and the first patterned spacer and between the black matrix and the second patterned spacer.

13. The LCD device according to claim 12, further comprising a common electrode formed between the color filter layer and the first patterned spacer and between the color filter layer the second patterned spacer.

14. The LCD device according to claim 13, further comprising an overcoat layer formed between the color filter layer and the common electrode.

15. The LCD device according to claim 1, further comprising a color filter layer formed between the second substrate and the first and second patterned spacers.

16. The LCD device according to claim 1, further comprising a common electrode on the first substrate, the common electrode being spaced apart from the pixel electrode.

17. The LCD device according to claim 1, wherein the data line includes a first layer, a second layer and a third layer such that the first layer is formed of a same layer as the active layer, the second layer is formed of a same layer as the ohmic contact layer, and the third is formed of a same layer as the source and drain electrodes.

18. A method of fabricating a liquid crystal display (LCD) device, comprising:

forming a gate line and a gate electrode extending from the gate line on a first substrate;

forming a gate insulating layer on the gate line and the gate electrode;

forming a data line on the gate insulating layer to define a pixel region with the gate line, an active layer on the gate insulating layer, an ohmic contact layer on the active layer, source and drain electrodes on the ohmic contact layer, and first and second protrusions on the gate insulating layer;

forming a passivation layer having a drain contact hole to cover the data line, the source and drain electrodes and the first and second protrusions, the drain contact hole exposing the drain electrode;

forming a pixel electrode connected to the drain electrode through the drain contact hole on the passivation layer;

forming first and second patterned spacers on a second substrate facing the first substrate;

attaching the first and second substrates, wherein the first and second patterned spacers face the first and second protrusions, respectively; and

forming a liquid crystal layer between the first and second substrates.

19. The method according to claim 18, wherein forming the data line, the active and ohmic contact layers, the source and drain electrodes and the first and second protrusions includes:

sequentially forming an intrinsic silicon layer, an impurity-doped silicon layer and a metal layer on the gate insulating layer;

forming a photoresist (PR) layer on the metal layer;

exposing the PR layer using a mask having a transmissive area, a half-transmissive area and a blocking area, wherein the transmissive area corresponds to the data line, the source and drain electrodes and the first protrusion, the half-transmissive area corresponds to the second protrusion and a hole between the source and drain electrodes;

developing the PR layer to form a first PR pattern corresponding to the transmissive area and a second PR pattern corresponding to the half-transmissive area and expose the metal layer between the transmissive area and the half-transmissive area, wherein the first PR pattern has a thickness greater than the second PR pattern;

forming the data line, and the first and second protrusions by sequentially etching the metal layer, the impurity-doped silicon layer and the intrinsic silicon layer, wherein the data line and the first and second protrusions each include a triple-layered structure, and the metal, impurity-doped silicon, intrinsic silicon layers correspond-to the blocking area;

removing the second PR pattern;

etching the metal layer and the ohmic contact layer to form the active layer on the gate insulating layer, the ohmic contact layer on the active layer and the source and drain electrodes on the ohmic contact layer, and the second protrusion including a single-layered structure, wherein the hole between the source and drain electrodes exposing the active layer; and

removing the first PR pattern.

20. The method according to the claim 19, wherein the first protrusion includes a first height and the second protrusion includes a second height, the first height being greater than the second height.

21. The method according to the claim 20, wherein the first patterned spacer and the second patterned spacer have substantially in a same height such that the first patterned spacer contacts the first protrusion and the second patterned spacer is separated from the second protrusion.

22. The method according to the claim 21, wherein the second patterned spacer is separated from the second protrusion by a gap less than about 0.3 μ

m.

23. The method according to the claim 19, wherein the data line includes first, second and third layers and the first protrusion includes fourth, fifth and sixth layers, such that the first and fourth layers are formed of a same layer as the active layer, the second and fifth layers are formed of a same layer as the ohmic contact layer, and the third and sixth layers are formed of a same layer as the source and drain electrodes.

24. The method according to claim 19, wherein the second protrusion is formed of a same layer as the active layer.

25. The method according to claim 19, wherein the first and second protrusions are arranged over the gate line.

26. The method according to claim 19, further comprising forming a black matrix between the second substrate and the first and second patterned spacers, wherein the black matrix corresponds to the gate and data lines.

27. The method according to claim 26, further comprising forming a color filter layer formed between the black matrix and the first and second patterned spacers.

28. The method according to claim 27, further comprising forming a common electrode formed between the color filter layer and the first and second patterned spacers.

29. The method according to claim 28, further comprising forming an overcoat layer formed between the color filter layer and the common electrode.

30. The method according to claim 19, further comprising forming a color filter layer formed between the second substrate and the first and second patterned spacers.

31. The method according to claim 19, further comprising forming a common electrode formed between the second substrate and the first and second patterned spacers.

32. The method according to claim 19, further comprising forming a common electrode on the first substrate, the common electrode being spaced apart from the pixel electrode.