Selective electroless-plated copper metallization

• US 20070085213A1
• Filed: 12/14/2006
• Published: 04/19/2007
• Est. Priority Date: 01/18/2000
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Ahn, Kie
• Application Number:
  US11/639,020
• Publication Number:
  US 20070085213A1
• Time in Patent Office: Days
• US Class Current: 257/762
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/4821 Bridge structure with air gap
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate to a thickness of less than 15 nanometers (nm). A number of via holes is defined above the seed layer. A layer of copper is deposited over the seed layer using electroless plating to fill the via holes to a top surface of the patterned photoresist layer. The method can be repeated any number of times, forming second, third and fourth layers of copper. The photoresist layers along with the seed layers in other regions can then be removed, such as by oxygen plasma etching, such that a chemical mechanical planarization process is avoided.

Claims

1. An electronic circuit, comprising:

a plurality of individual electrical devices interconnected by a plurality of metallic conductor lines;

a plurality of electrical contact areas on a top surface of the plurality of individual electric devices;

each of the plurality of electrical contact areas in contact with a first metallic layer;

the metallic layer in contact with a plurality of substantially vertical metal columns;

a top surface of the substantially vertical metal columns in contact with at least one of a second metallic layer and a portion of a bottom surface of a plurality of substantially horizontal metal lines; and

a diffusion barrier layer covering substantially the entirety of a top surface, side surfaces and all portions of the bottom surface not in contact with the top surface of the vertical metal columns of the plurality of substantially horizontal metal lines, and the diffusion barrier layer covering substantially the entirety of sidewalls of the vertical metal columns.

2. The electronic circuit of claim 1, wherein the plurality of substantially vertical metal columns are separated from each other by a gas, forming air bridges.

3. The electronic circuit of claim 1, wherein the diffusion barrier layer has a thickness of less than 8.0 nanometers (nm).

4. The electronic circuit of claim 1, wherein the first and second metallic layers have a thickness of less than 15 nanometers (nm).

5. The electronic circuit of claim 1, wherein the first and second metallic layers have a thickness of less than 5 nanometers (nm).

6. The electronic circuit of claim 1, wherein the first and second metallic layers includes a discontinuous island structure having islands less than 50 nanometers (nm) in diameter.

7. The electronic circuit of claim 1, wherein the substantially vertical metal columns and the substantially horizontal metal lines include copper.

8. The electronic circuit of claim 1, wherein the first and second metallic layers are formed of a material selected from a list consisting of palladium (Pd), copper (Cu), aluminum (Al), platinum (Pt), and combinations thereof.

9. The electronic circuit of claim 1, wherein the first metallic layer only contacts the plurality of electrical contact areas on the top surface of the individual electric devices.

10. The electronic circuit of claim 1, wherein the plurality of electronic devices are disposed in a substrate.

11. The electronic circuit of claim 10, wherein the substrate is a semiconducting material and the electronic circuit is an integrated circuit.

12. The electronic circuit of claim 1, wherein each of the plurality of substantially vertical metal columns is directly above one of the plurality of electrical contact areas on a top surface of the plurality of individual electrical devices.

13. The electronic circuit of claim 1, wherein the diffusion barrier layer comprises tungsten, silicon and nitrogen.

14. An integrated circuit, comprising:

a substrate including a plurality of transistors each having electrical contact areas;

individual ones of the plurality of transistors electrically interconnected by air bridge conductors comprising;

a plurality of metallic regions formed on the electrical contact areas of the plurality of transistors including a layer comprising at least one of palladium (Pd) and copper (Cu) having a thickness of less than 15 nanometers (nm);

each of the plurality of metallic regions contacting a vertical copper via formed above and contacting a bottom portion of one of a plurality of horizontal copper interconnect line; and

a diffusion barrier layer comprising surrounding the vertical copper vias and the horizontal copper interconnect except for the top and bottom surfaces of the vertical copper vias and the bottom contact points between the horizontal copper interconnect lines and the top surface of the vertical copper vias.

15. The integrated circuit of claim 14, wherein the diffusion barrier has a thickness of less than 8.0 nanometers (nm).

16. The integrated circuit of claim 15, wherein the diffusion barrier includes a graded composition of Tungsten Silicon Nitride (WSixNy), and wherein x varies from 2.0 to 2.5.

17. The integrated circuit of claim 14, wherein the metallic regions formed on the electrical contact areas of the plurality of transistors comprises unconnected islands of palladium between the lower surface of the vertical copper vias and the contact regions of the plurality of transistors.

18. An integrated circuit, comprising:

a plurality of devices formed in a semiconductor substrate;

a dielectric layer disposed over the semiconductor substrate including a plurality of contact holes;

a first metallic layer contacting portions of a surface of the semiconductor substrate exposed by the plurality of contact holes in the dielectric layer;

each of the plurality of contact holes including a substantially vertical metal column contacting the first metallic layer and extending above a top surface of the dielectric layer;

a second metallic layer contacting a top portion of the substantially vertical metal columns;

a plurality of substantially horizontal metal lines formed above and contacting the second metallic layer proximate to the top of the substantially vertical metal columns;

a diffusion barrier covering substantially the entirety of a top surface, a side surface and portions of a bottom surface of the substantially horizontal metal lines not in contact with the second metallic layer; and

the diffusion barrier covering substantially the entirety of portions of a sidewall of the substantially vertical metal columns not in contact with the dielectric layer.

19. The integrated circuit of claim 18, wherein the first and second metallic layers include at least one of palladium (Pd) and copper (Cu).

20. The integrated circuit of claim 18, wherein the first and second metallic layers have a barely continuous web within the contact holes, with a thickness from of 3 to 5 nanometers.

21. The integrated circuit of claim 18, wherein the first metallic layer comprises a discontinuous layer within each of the contact holes.

22. The integrated circuit of claim 21, wherein the first metallic layer comprises a plurality of non-connected islands within each of the contact holes.

23. The integrated circuit of claim 18, wherein the substantially vertical metal columns comprise copper.

24. The integrated circuit of claim 18, wherein the diffusion barrier comprises tungsten silicon nitride.

25. The integrated circuit of claim 18, wherein the diffusion barrier has a thickness of less than 8.0 nanometers.

26. The integrated circuit of claim 25, wherein the diffusion barrier comprises a graded composition of (WSixNy), and wherein x varies from 2.0 to 2.5.

27. An integrated circuit, comprising:

a plurality of devices formed in a semiconductor substrate;

a dielectric layer disposed over the semiconductor substrate including a plurality of contact holes;

a first metallic layer contacting portions of a surface of the semiconductor substrate exposed by the plurality of contact holes in the dielectric layer;

each of the plurality of contact holes including a substantially vertical metal column contacting the first metallic layer and extending above a top surface of the dielectric layer to form a first plurality of substantially vertical metal columns;

a second metallic layer contacting a top portion of each of the first plurality of substantially vertical metal columns;

a first plurality of substantially horizontal metal lines formed above and contacting the second metallic layer proximate to the top of the first plurality of substantially vertical metal columns;

a third metallic layer contacting a portion of a top surface of the first plurality of substantially horizontal metal lines;

a second plurality of substantially vertical metal columns disposed contacting the third metallic layer and the top surface of the substantially horizontal metal lines;

a fourth metallic layer contacting a top portion of each of the second plurality of substantially vertical metal columns;

a second plurality of substantially horizontal metal lines formed above and contacting the fourth metallic layer proximate to the top of the second plurality of substantially vertical metal columns; and

a diffusion barrier covering substantially the entirety of any portion of the first and second plurality of substantially vertical columns not in directly contact with the dielectric layer or the first or second substantially horizontal metal lines, and the diffusion barrier covering substantially the entirety of any portion of the first and second substantially horizontal metal lines not in contact with the first and second substantially vertical columns.

28. The integrated circuit of claim 27, wherein each of the metallic layers comprise palladium (Pd) or copper (Cu), and have a thickness in the range of 3 to 10 nanometers.

29. The integrated circuit of claim 28, wherein the first metallic layer is confined within the contact holes and comprises a discontinuous layer.

30. The integrated circuit of claim 27, wherein the first and second substantially vertical metal columns comprise copper.

31. The integrated circuit of claim 27, wherein the diffusion barrier comprises tungsten silicon nitride.

32. The integrated circuit of claim 27, wherein the diffusion barrier has a thickness of about 2.0-8.0 nanometers.

33. The integrated circuit of claim 27, wherein the diffusion barrier comprises a graded composition of (WSixNy), wherein x varies from 2.0 to 2.5.