Differential amplifier, digital-to-analog converter, and display device

• US 20070085608A1
• Filed: 09/26/2006
• Published: 04/19/2007
• Est. Priority Date: 09/27/2005
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Tsuchi, Hiroshi, Iriguchi, Masao
• Granted Patent: US 7,623,054 B2
• Time in Patent Office: Days
• US Class Current: 330/260
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H03F 2203/45616 the IC comprising more than one switch, which are not cross coupled
• CPC Class Codes: H03F 2203/45631 the LC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45656 the LC comprising one diode of a current mirror, i.e. forming an asymmetrical load
• CPC Class Codes: H03F 2203/45682 the LC comprising one or more op-amps
• CPC Class Codes: H03F 2203/45728 the LC comprising one switch
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03M 1/765 using a single level of switches which are controlled by unary decoded digital signals

Abstract

Disclosed is a differential amplifier of a multi-level output type comprising a load circuit including a diode-connected first transistor with a source thereof connected to a power supply and a second transistor with a source thereof connected to the power supply and connected to a gate of the first transistor through a capacitor, a differential pair including a third transistor and a fourth transistor with sources thereof connected in common and drains thereof connected to drains of the first and second transistors, respectively, a current source for supplying a current to the differential pair, a first switch connected between a gate of the second transistor and a drain of the fourth transistor, an amplifier with an input thereof connected to a drain of the second transistor and an output thereof connected to an output terminal, a second switch connected between a gate of the fourth transistor and a first input terminal, a third switch connected between the gate of the fourth transistor and a third input terminal, a fourth switch connected between a gate of the third transistor and a second input terminal, and a fifth switch connected between the gate of the third transistor and the output terminal. Switching control between a first state where the first, second and fourth switches are turned on and the third and fifth switches are turned off and a second state where the first and second fourth switches are turned off and the third and fifth switches are turned on is performed.

Claims

1. A differential amplifier comprising:

first and second input terminals and an output terminal;

a differential pair having a pair of inputs thereof connected to said first terminal and said second input terminal, respectively, said differential pair for performing voltage-to-current conversion of voltages at said first and second input terminals to output differential currents to first and second nodes, respectively;

a first current source for supplying a current to said differential pair;

a first load circuit connected to said first node, said first load circuit for performing current-to-voltage conversion of a current at said first node to a voltage at a third node;

a second load circuit connected to said second node, said second load circuit for reversibly performing mutual conversion between a current at said second node and a voltage at a fourth node and for supplying a voltage signal to a fifth node;

a capacitance element connected between said third node and said fourth node; and

an amplifier circuit for charging or discharging said output terminal based on the voltage signal at said fifth node;

wherein responsive to a control signal, said differential amplifier is subjected to switching control between first and second states, wherein in said first state,

a first signal is supplied to said first input terminal,

a second signal is supplied to said second input terminal, and

a potential difference between the voltages at said third and fourth nodes output by said first and second load circuits, respectively, are stored in said capacitance element; and

wherein

in said second state,

a third signal is supplied to said second input terminal,

a signal at said output terminal is fed back to said first input terminal, and

the potential difference stored in said capacitance element in said first state is held and a voltage signal is output to said fifth node based on the potential difference.

3. The differential amplifier according to claim 1, wherein said third signal is identical with said first signal.

5. The differential amplifier according to claim 1, wherein

said first load circuit includes a first transistor and said second load circuit includes a second transistor;

a drain of said first transistor is connected to said first node;

a gate of said first transistor is connected to said third node;

a drain of said second transistor is connected to said second and fifth nodes;

a gate of said second transistor is connected to said fourth node;

said gate of said first transistor and said drain of said first transistor are short-circuited;

said gate of said second transistor and said drain of said second transistor are connected or interrupted; and

said first and second transistors constitute a current mirror load circuit, and amplification and output are performed based on the voltage signal at said fifth node.

6. The differential amplifier according to claim 1, wherein

said first load circuit includes first and fifth transistors and said second load circuit includes second and sixth transistors;

a drain of said fifth transistor is connected to said first node;

a gate of said first transistor is connected to said third node;

a drain of said sixth transistor is connected to said second node;

a gate of said second transistor is connected to said fourth node;

a drain of said second transistor and a source of said sixth transistor are connected to said fifth node;

a gate of said first transistor and said drain of said fifth transistor are short-circuited;

a drain of said first transistor and a source of said fifth transistor are short-circuited;

said gate of said second transistor and said drain of said sixth transistor are connected or interrupted by the control signals; and

said first, second, fifth, and sixth transistors constitute a cascode-type current mirror load circuit, and amplification for output are performed based on the voltage signal at said fifth node.

8. The differential amplifier according to claim 1, comprising:

a second current source and a sixth switch connected in parallel with said first current source.

9. The differential amplifier according to claim 8, wherein said sixth switch is set in an ON state during said first period and is set in an OFF state during said second period.

10. The differential amplifier according to claim 1, wherein output switches are provided between said output terminal of said differential amplifier and an external load.

11. The differential amplifier according to claim 10, wherein

said output switches are set in an OFF state during said first period;

and

said output switches are set in an ON state during said second period.

12. A digital-to-analog conversion circuit comprising:

the differential amplifier as set fourth in claim 1;

a resistor array connected in series between a higher first potential and a lower second potential; and

a selection circuit for receiving voltages at taps of said resistor array and selecting voltages to be supplied to the first, second, and third signals, respectively, based on a selection signal.

13. A display device including amplifier circuits each for receiving a gray scale voltage and driving a data line connected to a display element, wherein each of said amplifier circuits includes:

the differential amplifier as set fourth in claim 1.

14. The display device according to claim 13, wherein the data line comprises a plurality of data lines, said data lines including first data lines and second data lines adjacent to said first data lines respectively;

and

said display device comprises a plurality of said differential amplifiers including first differential amplifiers for charging and second differential amplifiers for discharging;

first output switches respectively provided between each of said first differential amplifiers and each of said first data lines;

second output switches respectively provided between each of said first differential amplifiers and each of said second data lines;

third output switches respectively provided between each of said second differential amplifiers and each of said first data lines; and

fourth output switches respectively provided between each of said second differential amplifiers and each of said second data lines;

wherein

during a predetermined data output period, said second and third output switches are set in an OFF state and said first and fourth output switches are set in an ON state; and

during a data output period subsequent to the predetermined data output period, said first and fourth output switches are set in an OFF state and said second and third output switches are set in an ON state.

15. The display device according to claim 13, wherein

the data line comprises a plurality of data lines, and said data lines includes first data lines and second data lines adjacent to said first data lines, respectively;

and

said display device comprises a plurality of said differential amplifiers including first differential amplifiers for charging and second differential amplifiers for discharging;

first output switches respectively provided between each of said first differential amplifiers and each of said first data lines;

second output switches respectively provided between each of said first differential amplifiers and each of said second data lines;

third output switches respectively provided between each of said second differential amplifiers and each of said first data lines; and

fourth output switches respectively provided between each of said second differential amplifiers and each of said second data lines;

wherein

control is performed so that during a predetermined data output period, said second and third output switches are set in an OFF state, and said first and fourth output switches are turned on after having been set in an OFF state during a predetermined period from a start of the data output period; and

during a data output period subsequent to the predetermined data output period, said first and fourth output switches are set in an OFF state, and said second and third output switches are turned on after having been set in an OFF state during the predetermined period after a start of the data output period.

2. A differential amplifier comprising:

first and second input terminals and an output terminal;

a differential pair having a pair of inputs thereof connected to said first terminal and said second input terminal, respectively, said differential pair for performing voltage-to-current conversion of voltages at said first and second input terminals to output differential currents to first and second nodes, respectively;

a first current source for supplying a current to said differential pair;

a first load circuit connected to said first node, said first load circuit for performing current-to-voltage conversion of a current at said first node to a voltage at a third node;

a second load circuit connected to said second node, said second load circuit for reversibly performing mutual conversion between a current at said second node and a voltage at a fourth node and for supplying a voltage signal to a fifth node;

a capacitance element connected between said third node and said fourth node; and

an amplifier circuit for charging or discharging said output terminal based on the voltage signal at said fifth node;

wherein

a data output period of said differential amplifier includes first and second periods and responsive to a control signal, switching control between said first period and said second period is performed, wherein

in said first period,

a first signal is supplied to said first input terminal of said differential pair through a fourth switch in an on state;

a second signal is supplied to said second input terminal of said differential pair through a second switch in the on state;

said second and fourth nodes are short-circuited by a first switch in the on state; and

a potential difference between said third and fourth nodes is stored in said capacitance element; and

wherein

in said second state,

said first, second, and fourth switches are all turned off,

said output terminal is feedback connected to said first input terminal of said differential pair through a fifth switch in the on state, and

a third signal is supplied to said second input terminal of said differential pair through a third switch in the on state.

4. The differential amplifier according to claim 2, wherein said third signal is identical with said first signal.

7. The differential amplifier according to claim 2, wherein

said first switch comprises a third transistor and

said differential amplifier comprises a fourth transistor with a drain thereof and with a source thereof short-circuited, said fourth transistor arranged between said third transistor and said fourth node;

wherein

a first control signal is supplied to a gate of said third transistor,

a second control signal is supplied to a gate of a fourth transistor, and

the second control signal is an inverted signal of the first control signal.

16. A differential amplifier comprising:

first through third input terminals and an output terminal;

a load circuit including;

a first transistor with a first end thereof connected to a first power supply;

a second transistor with a first end thereof connected to said first power supply; and

a capacitor connected between a control terminal of said first transistor and a control terminal of said second transistor;

a differential pair including third and fourth transistors with first ends thereof connected in common and with second ends thereof connected to second ends of said first and second transistors, respectively;

a control terminal of said first transistor being connected to the second terminal of said third transistor;

a current source connected between a second power supply and the commonly coupled first ends of said third and fourth transistors, said current source for supplying a current to said differential pair;

a first switch connected between said control terminal of said second transistor and the second end of said fourth transistor;

an amplifier with an input thereof connected to the second end of said second transistor and an output thereof connected to said output terminal;

a second switch connected between a control terminal of said fourth transistor and said first input terminal and a third switch connected between said control terminal of said fourth transistor and said third input terminal;

a fourth switch connected between a control terminal of said third transistor and said second input terminal; and

a fifth switch connected between said control terminal of said third transistor and said output terminal;

said control terminal of said first transistor being connected to the second end of said third transistor;

said first through fifth switches being subject to switching control between a first state and a second state, wherein

in said first state, said first, second, and fourth switches are set in an ON state and said third and fifth switches are set in an OFF state; and

in said second state, said first, second, fourth switches being set in an OFF state and said third and fifth switches being set in an ON state.

17. The differential amplifier according to claim 16, wherein said third input terminal is identical with said second input terminal.

18. The differential amplifier according to claim 16, wherein said load circuit includes fifth and sixth transistors cascode-connected to said first and second transistors, respectively, and said fifth and sixth transistor are connected to the second ends of said third and fourth transistors, respectively.

19. The differential amplifier according to claim 16, comprising a sixth switch provided between said control terminal of said second transistor and the second end of said fourth transistor,

said sixth switch being subject to on/off control by a control terminal thereof and having first and second ends short-circuited, said sixth switch being connected in series with said first switch.

20. The differential amplifier according to claim 16, comprising a series circuit provided between said second current source and the commonly coupled first ends of said third and fourth transistor, in parallel with said current source, said series circuit comprising a second current source and a switch.