Probabilistic error correction in multi-bit-per-cell flash memory

• US 20070086239A1
• Filed: 01/26/2006
• Published: 04/19/2007
• Est. Priority Date: 10/17/2005
• Status: Active Grant

• Current Assignee: Ramot at Tel Aviv University Limited (Tel Aviv University)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Alrod, Idan, Lasser, Menahem, Sharon, Eran, Murin, Mark, Litsyn, Simon
• Granted Patent: US 7,526,715 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1024 Identification of the type of error
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H03M 13/458 by updating bit probabilities or hard decisions in an iterative fashion for convergence to a final decoding result

Abstract

Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Claims

1. A method of reading a plurality of data bits that are stored in a memory that includes a plurality of multi-bit cells, the storing being effected by computing a plurality of parity bits that correspond to the data bits and then storing the data bits and the parity bits as stored bits in the cells of the memory, with a respective plurality of the stored bits being stored in each of the cells, the method comprising the steps of:

(a) reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and

(b) correcting said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is effected at least in part in accordance with a priori estimates of respective probabilities of at least two of said read bits being erroneous, wherein at least one said estimate is different from at least one other said estimate.

2. The method of claim 1, wherein at least two of said a priori estimates are for said read bits of a common one of the cells.

3. The method of claim 1, wherein at least two of said a priori estimates are for said read bits of different cells.

4. The method of claim 1, wherein said a priori probabilities depend on respective significances of said read bits.

5. The method of claim 1, wherein said a priori probabilities depend on respective bit pages of said read bits.

6. A controller, for a memory that includes a plurality of multi-bit cells, that reads data stored in the memory using the method of claim 1.

7. A memory device comprising:

(a) a memory that includes a plurality of multi-bit cells; and

(b) the controller of claim 6 for controlling said memory.

8. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a memory that includes a plurality of multi-bit cells and wherein are stored a plurality of data bits, the data bits being stored by computing a plurality of parity bits that correspond to the data bits and then storing the data bits and the parity bits as stored bits in the cells of the memory, with a respective plurality of the stored bits being stored in each of the cells, the computer-readable code comprising:

(a) program code for reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and

(b) program code for correcting said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is effected at least in part in accordance with a priori estimates of respective probabilities of at least two of said read bit being erroneous, wherein at least one said estimate is different from at least one other said estimate.

9. A method of reading a plurality of data bits that are stored in a memory that includes a plurality of multi-bit cells, the storing being effected by computing a plurality of protected bits that correspond to the data bits and then storing the protected bits in the cells of the memory, with a respective plurality of the protected bits being stored in each of the cells, the method comprising the steps of:

(a) reading the cells, thereby obtaining, for each cell, a respective plurality of read protected bits; and

(b) recovering the data bits from the read protected bits, wherein said recovering is effected at least in part in accordance with a priori estimates of respective probabilities of at least two of said read protected bits being erroneous, wherein at least one said estimate is different from at least one other said estimate.

10. The method of claim 9, wherein at least two of said a priori estimates are for said read protected bits of a common one of the cells.

11. The method of claim 9, wherein at least two of said a priori estimates are for said read protected bits of different cells.

12. The method of claim 9, wherein said a priori probabilities depend on respective significances of said read protected bits.

13. The method of claim 9, wherein said a priori probabilities depend on respective bit pages of said read protected bits.

14. A controller, for a memory that includes a plurality of multi-bit cells, that reads data stored in the memory using the method of claim 9.

15. A memory device comprising:

(a) a memory that includes a plurality of multi-bit cells; and

(b) the controller of claim 14 for controlling said memory.

16. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a memory that includes a plurality of multi-bit cells and wherein are stored a plurality of data bits, the data bits being stored by computing a plurality of protected bits that correspond to the data bits and then storing the protected bits in the cells of the memory, with a respective plurality of the protected bits being stored in each of the cells, the computer-readable code comprising:

(a) program code for reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and

(b) program code for recovering the data bits from the read protected bits, wherein said recovering is effected at least in part in accordance with a priori estimates of respective probabilities of at least two of said read protected bits being erroneous, wherein at least one said estimate is different from at least one other said estimate.

17. A method of reading a plurality of data bits that are stored in a memory that includes a plurality of multi-bit cells, the storing being effected by computing a plurality of parity bits that correspond to the data bits and then storing the data bits and the parity bits as stored bits in the cells of the memory, with a respective plurality of the stored bits being stored in each of the cells, the method comprising the steps of:

(a) reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and

(b) correcting said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is effected in accordance with respective probabilities, of at least two of said read bits being erroneous, that are based only on at least one aspect of said read bits, said at least one aspect including an aspect selected from the group consisting of respective significances of said read bits and respective bit pages of said read bits, wherein at least one said probability is different from at least one other said probability.

18. A controller, for a memory that includes a plurality of multi-bit cells, that reads data stored in the memory using the method of claim 17.

19. A memory device comprising:

(a) a memory that includes a plurality of multi-bit cells; and

(b) the controller of claim 18 for controlling said memory.

20. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a memory that includes a plurality of multi-bit cells and wherein are stored a plurality of data bits, the data bits being stored by computing a plurality of parity bits that correspond to the data bits and then storing the data bits and the parity bits as stored bits in the cells of the memory, with a respective plurality of the stored bits being stored in each of the cells, the computer-readable code comprising:

(a) program code for reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and

(b) program code for correcting said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is effected in accordance with respective probabilities, of at least two of said read bits being erroneous, that are based only on at least one aspect of said read bits, said at least one aspect including an aspect selected from the group consisting of respective significances of said read bits and respective bit pages of said read bits, wherein at least one said probability is different from at least one other said probability.

21. A method of reading a plurality of data bits that are stored in a memory that includes a plurality of multi-bit cells, the storing being effected by computing a plurality of protected bits that correspond to the data bits and then storing the protected bits in the cells of the memory, with a respective plurality of the protected bits being stored in each of the cells, the method comprising the steps of:

(a) reading the cells, thereby obtaining, for each cell, a respective plurality of read protected bits; and

(b) recovering the data bits from the read protected bits, wherein said recovering is effected in accordance with respective probabilities, of at least two of said read protected bits being erroneous, that are based only on at least one aspect of said read protected bits, said at least one aspect including an aspect selected from the group consisting of respective significances of said read protected bits and respective bit pages of said read protected bits, wherein at least one said probability is different from at least one other said probability.

22. A controller, for a memory that includes a plurality of multi-bit cells, that reads data stored in the memory using the method of claim 21.

23. A memory device comprising:

(a) a memory that includes a plurality of multi-bit cells; and

(b) the controller of claim 22 for controlling said memory.

24. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a memory that includes a plurality of multi-bit cells and wherein are stored a plurality of data bits, the data bits being stored by computing a plurality of protected bits that correspond to the data bits and then storing the protected bits in the cells of the memory, with a respective plurality of the protected bits being stored in each of the cells, the computer-readable code comprising:

(a) program code for reading the cells, thereby obtaining, for each cell, a respective plurality of read protected bits; and

(d) program code for recovering the data bits from said read protected bits, wherein said recovering is effected in accordance with respective probabilities, of at least two of said read protected bits being erroneous, that are based only on at least one aspect of said read protected bits, said at least one aspect including an aspect selected from the group consisting of respective significances of said read protected bits and respective bit pages of said read protected bits, wherein at least one said probability is different from at least one other said probability.

25. A method of reading a plurality of data bits that are stored in a memory that includes a plurality of multi-bit cells, the storing being effected by computing a plurality of parity bits that correspond to the data bits and then storing the data bits and the parity bits as stored bits in the cells of the memory, with a respective plurality of the stored bits being stored in each of the cells, the method comprising the steps of:

(a) reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and

(b) correcting said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is effected in accordance with respective probabilities, of at least two of said read bits being erroneous, that are based only on respective values of said read bits, wherein at least one said probability is different from at least one other said probability.

26. A controller, for a memory that includes a plurality of multi-bit cells, that reads data stored in the memory using the method of claim 25.

27. A memory device comprising:

(a) a memory that includes a plurality of multi-bit cells; and

(b) the controller of claim 26 for controlling said memory.

28. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a memory that includes a plurality of multi-bit cells and wherein are stored a plurality of data bits, the data bits being stored by computing a plurality of parity bits that correspond to the data bits and then storing the data bits and the parity bits as stored bits in the cells of the memory, with a respective plurality of the stored bits being stored in each of the cells, the computer-readable code comprising:

(a) program code for reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and

(b) program code for correcting said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is effected in accordance with respective probabilities, of at least two of said read bits being erroneous, that are based only on respective values of said read bits, wherein at least one said probability is different from at least one other said probability.

29. A method of reading a plurality of data bits that are stored in a memory that includes a plurality of multi-bit cells, the storing being effected by computing a plurality of protected bits that correspond to the data bits and then storing the protected bits in the cells of the memory, with a respective plurality of the protected bits being stored in each of the cells, the method comprising the steps of:

(a) reading the cells, thereby obtaining, for each cell, a respective plurality of read protected bits; and

(b) recovering the data bits from the read protected bits, wherein said recovering is effected in accordance with respective probabilities, of at least two of said read protected bits being erroneous, that are based only on respective values of said read protected bits, wherein at least one said probability is different from at least one other said probability.

30. A controller, for a memory that includes a plurality of multi-bit cells, that reads data stored in the memory using the method of claim 29.

31. A memory device comprising:

(a) a memory that includes a plurality of multi-bit cells; and

(b) the controller of claim 30 for controlling said memory.

32. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a memory that includes a plurality of multi-bit cells and wherein are stored a plurality of data bits, the data bits being stored by computing a plurality of protected bits that correspond to the data bits and then storing the protected bits in the cells of the memory, with a respective plurality of the protected bits being stored in each of the cells, the computer-readable code comprising:

(a) program code for reading the cells, thereby obtaining, for each cell, a respective plurality of read protected bits; and

(d) program code for recovering the data bits from said read protected bits, wherein said recovering is effected in accordance with respective probabilities, of at least two of said read protected bits being erroneous, that are based only on respective values of said read protected bits, wherein at least one said probability is different from at least one other said probability.

33. A method of reading a plurality of data bits that are stored in a memory that includes a plurality of multi-bit cells, the storing being effected by computing a plurality of parity bits that correspond to the data bits and then storing the data bits and the parity bits as stored bits in the cells of the memory, with a respective plurality of the stored bits being stored in each of the cells, the method comprising the steps of:

(a) reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and

(b) correcting said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is effected in accordance with respective probabilities, of at least two of said read bits being erroneous, that are based at least in part on information obtained as a result of said reading, said information being confined to respective values of said read bits, wherein at least one said probability is different from at least one other said probability.

34. A controller, for a memory that includes a plurality of multi-bit cells, that reads data stored in the memory using the method of claim 33.

35. A memory device comprising:

(a) a memory that includes a plurality of multi-bit cells; and

(b) the controller of claim 34 for controlling said memory.

36. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a memory that includes a plurality of multi-bit cells and wherein are stored a plurality of data bits, the data bits being stored by computing a plurality of parity bits that correspond to the data bits and then storing the data bits and the parity bits as stored bits in the cells of the memory, with a respective plurality of the stored bits being stored in each of the cells, the computer-readable code comprising:

(a) program code for reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and

(b) program code for correcting said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is effected in accordance with respective probabilities, of at least two of said read bits being erroneous, that are based at least in part on information obtained as a result of said reading, said information being confined to respective values of said read bits, wherein at least one said probability is different from at least one other said probability.

37. A method of reading a plurality of data bits that are stored in a memory that includes a plurality of multi-bit cells, the storing being effected by computing a plurality of protected bits that correspond to the data bits and then storing the protected bits in the cells of the memory, with a respective plurality of the protected bits being stored in each of the cells, the method comprising the steps of:

(a) reading the cells, thereby obtaining, for each cell, a respective plurality of read protected bits; and

(b) recovering the data bits from the read protected bits, wherein said recovering is effected in accordance with respective probabilities, of at least two of said read protected bits being erroneous, that are based at least in part on information obtained as a result of said reading, said information being confined to respective values of said read protected bits, wherein at least one said probability is different from at least one other said probability.

38. A controller, for a memory that includes a plurality of multi-bit cells, that reads data stored in the memory using the method of claim 37.

39. A memory device comprising:

(a) a memory that includes a plurality of multi-bit cells; and

(b) the controller of claim 38 for controlling said memory.

40. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a memory that includes a plurality of multi-bit cells and wherein are stored a plurality of data bits, the data bits being stored by computing a plurality, of protected bits that correspond to the data bits and then storing the protected bits in the cells of the memory, with a respective plurality of the protected bits being stored in each of the cells, the computer-readable code comprising:

(a) program code for reading the cells, thereby obtaining, for each cell, a respective plurality of read protected bits; and

(d) program code for recovering the data bits from said read protected bits, wherein said recovering is effected in accordance with respective probabilities, of at least two of said read protected bits being erroneous, that are based at least in part on information obtained as a result of said reading, said information being confined to respective values of said read protected bits, wherein at least one said probability is different from at least one other said probability.