METHOD FOR CONTROLLED PROGRAMMING OF NON-VOLATILE MEMORY EXHIBITING BIT LINE COUPLING
First Claim
1. A method for programming non-volatile storage, comprising:
- applying a program voltage to at least first and second non-volatile storage elements in a set of non-volatile storage elements, the first and second non-volatile storage elements being coupled to respective first and second bit lines via respective first and second select gates;
partially inhibiting programming of the first non-volatile storage element during the program voltage by controlling a voltage applied to the first bit line;
inhibiting programming of the second non-volatile storage element during the program voltage by providing an inhibit voltage on the second bit line; and
adjusting a select gate voltage which is applied to the second select gate during a transition in the voltage applied to the first bit line during the program voltage.
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Accused Products
Abstract
The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.
69 Citations
28 Claims
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1. A method for programming non-volatile storage, comprising:
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applying a program voltage to at least first and second non-volatile storage elements in a set of non-volatile storage elements, the first and second non-volatile storage elements being coupled to respective first and second bit lines via respective first and second select gates;
partially inhibiting programming of the first non-volatile storage element during the program voltage by controlling a voltage applied to the first bit line;
inhibiting programming of the second non-volatile storage element during the program voltage by providing an inhibit voltage on the second bit line; and
adjusting a select gate voltage which is applied to the second select gate during a transition in the voltage applied to the first bit line during the program voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for programming non-volatile storage, comprising:
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controlling a rate of programming of a first non-volatile storage element, in a set of non-volatile storage elements, by controlling a voltage applied to a first bit line to which the first non-volatile storage element is coupled via a first select gate;
inhibiting programming of a second non-volatile storage element, in the set of non-volatile storage elements, by providing an inhibit voltage on a second bit line to which the second non-volatile storage element is coupled via a second select gate; and
adjusting a select gate voltage applied to the second select gate in accordance with a change in the voltage applied to the first bit line. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for programming non-volatile storage, comprising:
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applying a program voltage to at least first and second non-volatile storage elements in a set of non-volatile storage elements, the first and second non-volatile storage elements being coupled to respective first and second bit lines via respective first and second select gates;
applying a voltage to the first bit line;
applying a select gate voltage to the second select gate; and
adjusting the select gate voltage in accordance with a change in the voltage applied to the first bit line to maintain the second select gate closed. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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Specification