Tamper response system for integrated circuits
First Claim
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1. A tamper response system comprising:
- at least one sensor adapted to sense tamper activity; and
a tamper circuit coupled to receive tamper signals from the at least one sensor, the tamper circuit adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal.
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Abstract
A tamper response system to protect intellectual property is provided. In one embodiment, the tamper response system includes at least one sensor adapted to sense tamper activity and a tamper circuit. The tamper circuit is coupled to receive tamper signals from the at least one sensor. Moreover, the tamper circuit is adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal.
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Citations
32 Claims
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1. A tamper response system comprising:
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at least one sensor adapted to sense tamper activity; and
a tamper circuit coupled to receive tamper signals from the at least one sensor, the tamper circuit adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A tamper system comprising:
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at least one sensor adapted to sense tamper activity; and
a tamper circuit coupled to receive tamper signals from the at least one sensor, the tamper circuit adapted to erase information in at least one memory upon receipt of a tamper signal. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A tamper circuit comprising:
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a sensor input adapted to receive tamper signals from one or more sensors;
an FPGA control output adapted to send a FPGA clearance signal to an FPGA to clear the FPGA;
a memory erase output adapted to erase a memory in communication with the memory erase output; and
a control circuit adapted to process tamper signals received at the sensor input, the control circuit further adapted to send the FPGA clearance signal to the FPGA control output and to control the memory erase output based on the processed tamper signals. - View Dependent Claims (16, 17, 18, 19)
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20. A method of protecting data in a FPGA, the method comprising:
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sensing tamper activity; and
in response to the sensing of tamper activity, overwriting the FPGA. - View Dependent Claims (21, 22, 23, 24, 25, 26)
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27. A machine readable medium having instructions stored thereon for protecting digital information, the method comprising:
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processing tamper signals from one or more tamper sensors;
manipulating an interface clearance input on an FPGA to clear the FPGA of information based on the processed tamper signals; and
erasing at least one memory based on the processed tamper signals. - View Dependent Claims (28, 29, 30)
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31. A digital data tamper system, the system comprising:
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a means to detect tamper activity;
a means to clear at least one FPGA upon detection of tamper activity; and
a means to erase at least one memory upon detection of the tamper activity. - View Dependent Claims (32)
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Specification