SYSTEM, METHOD, AND APPARATUS FOR JITTER REDUCTION IN A VIDEO DECODER SYSTEM
First Claim
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1. A method for processing data, said method comprising:
- receiving a bitstream, said bitstream comprising a first data stream and a second data stream, wherein the first data stream comprises data that is intended to be consumed at a substantially constant bit rate; and
controlling the processing rate of the second data stream based at least in part on the rate of receipt of the first data stream.
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Abstract
In one embodiment, there is presented a method for processing data. The method comprises receiving a bitstream, said bitstream comprising a first data stream and a second data stream, wherein the first data stream comprises data that is intended to be consumed at a substantially constant bit rate; and controlling the processing rate of the second data stream based at least in part on the rate of receipt of the first data stream.
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Citations
17 Claims
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1. A method for processing data, said method comprising:
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receiving a bitstream, said bitstream comprising a first data stream and a second data stream, wherein the first data stream comprises data that is intended to be consumed at a substantially constant bit rate; and
controlling the processing rate of the second data stream based at least in part on the rate of receipt of the first data stream. - View Dependent Claims (2, 3, 4, 8)
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5. A method for processing data, said method comprising:
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receiving a bitstream, said bitstream comprising an audio stream and a video stream, wherein the audio stream comprises data that is intended to be consumed at a substantially constant bit rate and the video stream comprises data that is intended to be consumed at a varying bit rate; and
controlling the processing rate of the video stream based at least in part on the rate of receipt of the audio stream. - View Dependent Claims (6, 7)
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9. A circuit for providing data from a bitstream, said circuit comprising:
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a first circuit for reducing jitter in the bitstream due to variable delay in the delivery of the bitstream, thereby resulting in the bitstream with another delivery schedule; and
a second circuit for recovering a time base of the bitstream, based at least in part on time stamps in the bitstream with the another delivery schedule. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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Specification