High-Performance LDPC Coding for Digital Communications in a Multiple-Input, Multiple-Output Environment

• US 20070086539A1
• Filed: 10/18/2006
• Published: 04/19/2007
• Est. Priority Date: 10/19/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hocevar, Dale
• Granted Patent: US 7,668,248 B2
• Time in Patent Office: Days
• US Class Current: 375/267
• CPC Class Codes: H03M 13/1185 wherein the parity-check matrix comprises a part with a double-diagonal
• CPC Class Codes: H03M 13/1188 wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three
• CPC Class Codes: H03M 13/616 Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
• CPC Class Codes: H03M 13/6362 by puncturing
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0068 by puncturing
• CPC Class Codes: H04L 1/0643 block codes
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only

Abstract

Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is disclosed. Error correction coding according to a fixed-block size code, such as low density parity check (LDPC) coding, is implemented. A specific LDPC code with excellent error rate performance is disclosed.

Claims

1. A method of transmitting coded communications comprising the steps of:

receiving a block of payload data;

applying a low density parity check (LDPC) code to the block of payload data to encode the received block of payload data into a codeword, the LDPC code represented by a macro matrix arranged in block rows and block columns and in which each entry corresponds to either an 81×

81 zero-valued matrix or corresponds to an 81×

81 circularly shifted identity matrix to define a parity check matrix, wherein the columns of the parity check matrix correspond to input nodes and the rows of the parity check matrix correspond to parity check sums, wherein the macro matrix is represented by an ordering of rows and columns from an arrangement of;

57501150791032805570030243756140062535333500402066222800084250800697979565200065385772270064145230320045700779002565735120024616027511610

in which numerical values correspond to the shifts of the identity diagonal in each of the circularly shifted identity matrices, and in which blank matrix entries correspond to a zero-valued matrix;

modulating at least one carrier signal to produce a signal stream having symbols corresponding to the codeword; and

transmitting the signal stream over a communications channel.

2. The method of claim 1, further comprising:

separating the codeword into a plurality of datastreams;

 

wherein the modulating step comprises;

modulating at least one carrier signal to produce each of a plurality of signal streams having symbols corresponding to an associated encoded datastream;

 

and wherein the transmitting step comprises;

transmitting the plurality of signal streams over a communications channel.

3. The method of claim 1, wherein the modulating step modulates a plurality of subchannel carrier signals for each of the plurality of signal streams.

4. A transceiver for transmitting an encoded signal stream, comprising:

encoder circuitry, for encoding payload data according to a low density parity check (LDPC) code to the block of payload data to encode the received block of payload data into a codeword, the LDPC code represented by a macro matrix arranged in block rows and block columns and in which each entry corresponds to an 81×

81 zero-valued matrix or corresponds to an 81×

81 circularly shifted identity matrix to define a parity check matrix, wherein the columns of the parity check matrix correspond to input nodes and the rows of the parity check matrix correspond to parity check sums, wherein the macro matrix is represented by an ordering of rows and columns from an arrangement of;

57501150791032805570030243756140062535333500402066222800084250800697979565200065385772270064145230320045700779002565735120024616027511610

in which numerical values correspond to the shifts of the identity diagonal in each of the circularly shifted identity matrices, and in which blank matrix entries correspond to a zero-valued matrix;

a modulator, for modulating at least one carrier signal to produce a signal stream having symbols corresponding to the codeword; and

circuitry, for transmitting the modulated signal stream over a communications channel.

5. The transceiver of claim 4, further comprising:

parser circuitry for separating the encoded codeword into a plurality of datastreams; and

a plurality, of antennae;

 

wherein the modulator modulates at least one carrier signal according to each of the plurality of datastreams;

 

and wherein the transmitting circuitry comprises;

RF circuitry, for transmitting, modulated signals for each of the multiple datastreams over a corresponding one of the plurality of antennae, the modulated signals corresponding to codewords for the respective datastreams generated by the encoder circuitry.

6. The transceiver of claim 5, wherein the modulator comprises:

modulation circuitry, for modulating a plurality of subchannel carriers for each of the multiple datastreams according to the codewords.

7. A method of decoding coded communications, comprising the steps of:

demodulating a received signal;

to produce a datastream;

decoding the datastream with an error correcting code by applying the error correcting code to sequences of codewords in the datastream wherein the error correcting code is a low density parity check (LDPC) represented by a macro matrix arranged in block rows and block columns and in which each entry corresponds to an 81×

81 zero-valued matrix or corresponds to an 81×

81 circularly shifted identity matrix to define a parity check matrix, wherein the columns of the parity check matrix correspond to input nodes and the rows of the parity check matrix correspond to parity check sums, wherein the macro matrix is represented by an ordering of rows and columns from an arrangement of;

57501150791032805570030243756140062535333500402066222800084250800697979565200065385772270064145230320045700779002565735120024616027511610

in which numerical values correspond to the shifts of the identity diagonal in each of the circularly shifted identity matrices, and in which blank matrix entries correspond to a zero-valued matrix; and

forwarding the decoded datastream to a destination.

8. The method of claim 7, wherein the signal is received at each of a plurality of antennae;

wherein the demodulating, step comprises;

demodulating a signal received at each of a plurality, of antennae;

to produce a plurality of demodulated datastreams;

and further comprising after the demodulating step;

combining the plurality of demodulated datastreams into a datastream, arranged as a sequence of codewords, each codeword including information and parity portions.

9. A transceiver for receiving and decoding an encoded signal stream, comprising:

a demodulator, for demodulating at least one carrier signal to produce a signal stream having symbols corresponding to codewords; and

decoder circuitry, for decoding payload data from the codewords according to a low density parity check (LDPC) code, the LDPC code represented by a macro matrix arranged in block rows and block columns and in which each entry corresponds to either an 81×

81 zero-valued matrix or corresponds to an 81×

81 circularly shifted identity matrix to define a parity check matrix, wherein the columns of the parity check matrix correspond to input nodes and the rows of the parity check matrix correspond to parity check sums, wherein the macro matrix is represented by an ordering of rows and columns from an arrangement of;

57501150791032805570030243756140062535333500402066222800084250800697979565200065385772270064145230320045700779002565735120024616027511610

in which numerical values correspond to the shifts of the identity diagonal in each of the circularly shifted identity matrices, and in which blank matrix entries correspond to a zero-valued matrix.

10. The transceiver of claim 9, further comprising:

interface circuitry, coupled to a plurality of antennae to receive signals from each of the antennae;

 

wherein the demodulator comprises;

demodulating circuitry for demodulating a signal received from each of the plurality of antennae;

to produce a plurality of demodulated datastreams;

 

and further comprising;

circuitry, coupled to the demodulating circuitry, for combining the plurality of demodulated datastreams into the datastream applied to the decoder circuitry, the datastream arranged as a sequence of codewords, each codeword including information and parity portions.