Lithography process to reduce interference

• US 20070087291A1
• Filed: 10/18/2005
• Published: 04/19/2007
• Est. Priority Date: 10/18/2005
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Gau, Tsai-Sheng, Shin, Jaw-Jung, Chen, Chun-Kuang, Lin, Burn-Jeng, You, Jan-Wen
• Application Number:
  US11/252,499
• Publication Number:
  US 20070087291A1
• Time in Patent Office: Days
• US Class Current: 430/311
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/203 comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475

Abstract

A method and associated masks for carrying out a lithographic imaging process to reduce or avoid a strong interference effect in off-axis illumination, the method including providing a resist layer on a substrate; illuminating a first group of line patterns through a first mask on the resist layer; illuminating a second group of line patterns through a second mask on the resist layer, the second group of line patterns oriented nonparallel with respect to the first group of line patterns; and, developing the illuminated resist layer.

Claims

1. A method for patterning non-parallel resist lines comprising the steps of:

providing a resist layer on a substrate;

illuminating a first group of line patterns through a first mask on the resist layer;

illuminating a second group of line patterns through a second mask on the resist layer, the second group of line patterns oriented nonparallel with respect to the first group of line patterns; and

,

developing the illuminated resist layer.

2. The method of claim 1, wherein the first mask comprises an opaque portion for blocking illumination to an area on the resist layer comprising the second group of line patterns.

3. The method of claim 1, wherein the second group of line patterns comprises a gate pattern.

4. The method of claim 3, wherein the first group of line patterns is contiguous with a portion of the gate pattern.

5. The method of claim 1, wherein the steps of illuminating the first group and illuminating the second group comprises off-axis illumination.

6. The method of claim 5, wherein the off-axis illumination comprises quadrupole illumination.

7. The method of claim 1, wherein the second group of line patterns comprises lines forming an angle with respect to the first group of line patterns from greater than about 0 degrees to about 90 degrees.

8. The method of claim 1, wherein the first and second masks are selected from the group consisting of a binary mask and an attenuating phase shift mask.

9. The method of claim 1, wherein the step of illuminating the second group of line patterns is performed prior to the step of illuminating the group of line patterns.

10. The method of claim 1, wherein the steps of illuminating the first group and illuminating the second group comprises illumination methods selected from the group consisting of a scanning illumination and step and repeat illumination.

11. A method for patterning non-parallel resist lines comprising a gate electrode portion and conductive line portions comprising the steps of:

providing a resist layer on a substrate;

illuminating a conductive line pattern on the resist layer through a first mask;

illuminating a gate pattern on the resist layer through a second mask, the gate pattern oriented nonparallel with respect to the conductive line pattern; and

,

developing the illuminated resist layer.

12. The method of claim 11, wherein the first mask further comprises an illumination blocking portion for blocking illumination to an area on the resist layer comprising the gate pattern.

13. The method of claim 11, wherein the conductive line pattern comprises portions oriented perpendicular to the gate pattern.

14. The method of claim 11, wherein the steps of illuminating a conductive line pattern and illuminating a gat pattern comprise off-axis illumination.

15. The method of claim 14, wherein the off-axis illumination comprises quadrupole illumination.

16. The method of claim 11, wherein the conductive line pattern comprises lines forming an angle with respect to the gate pattern from greater than about 0 degrees to about 90 degrees.

17. The method of claim 11, wherein the first and second masks are selected from the group consisting of a binary mask and an attenuating phase shift mask.

18. The method of claim 11, wherein the step of illuminating the gate pattern is carried out prior to the step of illuminating the conductive line pattern.

19. The method of claim 11, wherein the steps of illuminating a conductive line pattern and illuminating a gate pattern comprises illumination methods selected from the group consisting of a scanning illumination and step and repeat illumination.

20. A method for patterning non-parallel resist lines comprising a gate electrode portion and conductive line portions comprising the steps of:

providing a resist layer on a substrate;

illuminating a gate pattern on the resist layer through a first mask in a first exposure process comprising off-axis illumination;

illuminating a conductive line pattern on the resist layer through a second mask in a second exposure process comprising off-axis illumination, the conductive line pattern oriented nonparallel with respect to the gate pattern; and

,

developing the illuminated resist layer.