Method of recycling an epitaxied donor wafer

• US 20070087526A1
• Filed: 03/21/2006
• Published: 04/19/2007
• Est. Priority Date: 10/18/2005
• Status: Abandoned Application

• Current Assignee: Soitec Silicon On Insulator Technologies SA (Soitec S.A.)
• Original Assignee: Soitec Silicon On Insulator Technologies SA (Soitec S.A.)
• Inventors: Guiot, Eric, Chhaimi, Nabil, Reynaud, Patrick
• Application Number:
  US11/386,967
• Publication Number:
  US 20070087526A1
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: H01L 21/02032 by reclaiming or re-processing
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

A method for forming a semiconductor structure comprising a thin layer of semiconductor material on a receiver wafer is disclosed. The method comprises removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the epitaxial layer from the donor wafer to the receiver wafer. The thickness removed during the surface preparation is adapted to enable formation of a new semiconductor structure from the remaining epitaxial portion of the donor wafer.

Claims

1. A method for producing two or more semiconductor structures using a single donor wafer, the method comprising the steps of:

providing a donor wafer comprising a support substrate, and a hetero-epitaxial layer comprising a buffer layer having a mesh parameter that is different from that of the support substrate, and at least one epitaxial layer of semiconductor material on the buffer layer;

transferring a portion of the at least one epitaxial layer to a receiver wafer to form a first semiconductor structure which comprises the receiver wafer and a semiconductor layer of the at least one epitaxial layer portion on the receiver wafer and second semiconductor structure which comprises the support substrate, the buffer layer and the remaining, non-transferred portion of the epitaxial layer;

treating the second semiconductor structure by removing at least part of the remaining, non-transferred portion of the epitaxial layer without removing the buffer layer to form a treated semiconductor structure having a surface that is sufficiently smooth for growth of at least one further epitaxial layer thereon; and

recycling the treated semiconductor structure for transfer of a portion of the further epitaxial layer.

2. The method according to claim 1, wherein the portion of the epitaxial layer is removed non-selectively.

3. The method according to claim 1, wherein the portion of the epitaxial layer is removed by polishing.

4. The method according to claim 3, wherein the polishing is chemical-mechanical polishing.

5. The method according to claim 4, wherein the portion of the epitaxial layer removed is a thickness of between about 0.1 and 4 μ

m.

6. The method according to claim 5, wherein the thickness of material is removed by a chemical-mechanical polishing with a polishing pad having a compressibility of about 2 to 15% and a slurry containing about 20% or more of silica particles having a size of about 70 to 210 nm so that the thickness removed from the epitaxial layer is between about 0.1 and 2 μ

m.

7. The method according to claim 1, wherein the second semiconductor structure includes a flange on an edge of the non-transferred portion of the epitaxial layer, the flange corresponding to a periphery of the transferred epitaxial portion, and wherein the removing step includes eliminating the flange.

8. The method according to claim 7, wherein the flange is eliminated by polishing or by local plasma etching.

9. The method according to claim 1, wherein the transferring comprises providing a weakened zone within the at least one epitaxial layer;

bringing the donor wafer and the receiver wafer into intimate contact; and

detaching the donor and the receiver wafers at the weakened zone to effect transfer of the at least one epitaxial layer portion from the donor wafer to the receiving substrate.

10. The method according to claim 9, wherein the second semiconductor structure includes a flange on an edge of the non-transferred portion of the epitaxial layer, the flange corresponding to a periphery of the transferred epitaxial portion, and wherein the removing step includes eliminating the flange by a degassing heat treatment.

11. The method according to claim 10, wherein the degassing heat treatment is an annealing stage performed at a temperature that is greater than 700°

C.

12. The method according to claim 10, further comprising cleaning a surface of the treated second semiconductor structure after the degassing heat treatment.

13. The method according to claim 12, wherein the cleaning is an RCA type cleaning.

14. The method according to claim 12, which further comprises forming an oxide layer on the surface of the treated second semiconductor structure after cleaning and eliminating the oxide layer to smooth the surface.

15. The method according to claim 14, wherein the oxide layer is eliminated by chemical etching.

16. The method according to claim 9, which further comprises providing an oxide layer on the epitaxial layer prior to bringing the donor wafer and receiving substrate into contact.

17. The method according to claim 9, which further comprises providing an overlayer upon the at least one epitaxial layer prior to bringing the donor wafer and receiving substrate into contact, wherein the overlayer has a mesh parameter that is essentially the same as that of the adjacent epitaxial layer.

18. The method according to claim 1, wherein the support substrate is an Si substrate, and the hetero-epitaxial layer comprises a buffer layer of SiGe, and an epitaxial layer of relaxed SiGe, and wherein the buffer layer is formed by epitaxial growth on the support substrate and has a Ge content which progressively increases from an interface with the support substrate.

19. The method according to claim 18, which further comprises providing an overlayer upon the at least one epitaxial layer prior to bringing the donor wafer and receiving substrate into contact, wherein the overlayer comprises a strained Si layer or a first layer of relaxed SiGe and a second layer of strained Si on the first layer.

20. The method according to claim 18, which further comprises providing an oxide layer on the epitaxial layer prior to bringing the donor wafer and receiving substrate into contact, wherein the oxide layer is silicon dioxide.