Memory system storing transformed units of data in fixed sized storage blocks

• US 20070088904A1
• Filed: 10/13/2005
• Published: 04/19/2007
• Est. Priority Date: 10/13/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sinclair, Alan
• Granted Patent: US 7,814,262 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A change in the amount of data to be stored that results from various encoding, compression, encryption or other data transformation algorithms, is handled by individually identifying distinct units of the transformed data and storing such units in physical succession within storage blocks of a memory system such as flash memory. The data being stored may come from a host system external to the memory system or from an application running on a processor within the memory system.

Claims

1. A non-volatile memory system, comprising:

a flash memory divided into distinct blocks of data storage elements, and

a controller connected with the flash memory and including a microprocessor operated by firmware, wherein the controller operates to transform data received within distinct units of logical addresses in a manner that changes the amount of data in at least some of the units that are stored in the storage element blocks and identifies storage locations of the transformed data by at least one data group having a physical boundary coincident with a logical boundary of the transformed data unit.

2. The memory system of claim 1, wherein the controller further operates to identify the storage locations of the transformed data by said at least one data group having a logical boundary coincident with a physical boundary of the storage element blocks.

3. The memory system of claim 2, wherein the controller further operates to avoid elimination of any boundaries of said at least one data group coincident with boundaries of the transformed units of data that are within boundaries of the blocks of storage elements.

4. The memory system of claim 1, wherein the controller further operates to transform the received data by at least one of encoding, compressing or encrypting the data.

5. The memory system of claim 4, wherein the controller further operates to transform the received data in a manner that reduces the amount of data that existed prior to the transformation.

6. The memory system of claim 4, wherein the controller further operates to transform the received data in a manner that increases the amount of data that existed prior to the transformation.

7. The memory system of claim 1, wherein the controller further operates to transform data received within distinct units of logical addresses that contain substantially equal amounts of data.

8. The memory system of claim 1, wherein the data received by the controller that are transformed originate outside of the memory system.

9. The memory system of claim 1, wherein the data received by the controller that are transformed originate with an application being executed by the controller.

10. The memory system of claim 1, wherein the distinct blocks contain the smallest number of data storage elements that are simultaneously erasable.

11. The memory system of claim 1, wherein the distinct blocks contain two or more units of storage elements that are linked together and individually contain the smallest number of storage elements that are simultaneously erasable.

12. The memory system of claim 1, wherein the storage elements include electrically conductive floating gates.

13. The memory system of claim 1, wherein the controller additionally includes a circuit dedicated to perform at least a portion of the transformation of the received data.

14. The memory system of claim 1, wherein the controller further operates to store more than one bit of data in individual ones of the storage elements.