Interface between subsystems in a digital processing device

• US 20070088933A1
• Filed: 10/13/2005
• Published: 04/19/2007
• Est. Priority Date: 10/13/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: OQO Incorporated (Audiotone Incorporated)
• Inventors: Kelley, Robert
• Granted Patent: US 8,234,482 B2
• Time in Patent Office: Days
• US Class Current: 712/38
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A subprocessor is used to interface between subsystems and to reduce the amount of dedicated hardware used to implement the subsystems in a hand-held computer. The subprocessor includes basic processing system resources such as random-access memory (RAM), read-only memory (ROM), a processor, input/output (I/O) facilities, etc. Selected functions in subsystems are achieved by firmware instructions executed by the subprocessor as opposed to a main processor that is also used in the computer. This approach can provide efficiencies such as low power consumption, less required space, less routing overhead, easier transfer of inter-subsystem information, and other advantages.

Claims

1. An apparatus for interfacing between first and second subsystems in a processing system, the apparatus comprising:

a main processor;

a subprocessor for executing instructions;

persistent memory directly coupled to the subprocessor and not to the main processor, the persistent memory including instructions for execution by the subprocessor;

a first interface for communicating between the subprocessor and the first subsystem;

a second interface for communicating between the subprocessor and the second subsystem; and

one or more instructions for exchanging information between the first and second subsystems.

2. The apparatus of claim 1, wherein a subsystem includes a user input control.

3. The apparatus of claim 2, wherein a user input control includes a keyboard.

4. The apparatus of claim 2, wherein a user input control includes a pointer control.

5. The apparatus of claim 1, wherein a subsystem includes power management.

6. The apparatus of claim 1, wherein a subsystem includes audible indicators.

7. The apparatus of claim 1, wherein a subsystem includes visual indicators.

8. The apparatus of claim 1, further comprising:

one or more instructions stored in the persistent memory for reading operations in a table of operations, wherein an operation has an attribute; and

one or more instructions stored in the persistent memory for using the operations in the table to perform communication between two subsystems.

9. The apparatus of claim 8, wherein the first subsystem includes a battery status subsystem and wherein the second subsystem includes an indication subsystem, the apparatus further comprising:

one or more operations stored in the table of operations for obtaining battery status information from the battery status subsystem; and

one or more operations stored in the table of operations for transferring the battery status information to the indication subsystem.

10. The apparatus of claim 9, wherein battery status information is stored in a memory location within the battery status subsystem.

11. An apparatus for interfacing between a plurality of subsystems in a processing system, the apparatus comprising:

a main processor;

a subprocessor for executing instructions;

persistent memory directly coupled to the subprocessor and not to the main processor, the persistent memory including instructions for execution by the subprocessor;

a plurality of interfaces for communicating between the plurality of subsystems; and

one or more instructions executable by the subprocessor for exchanging information between the subsystems.

12. A method for designing an electronic device in a system having N subsystems where the number of interconnections needed between subsystems is substantially a factor of N², wherein each subsystem includes functionality, the method comprising:

Identifying the maximum of the subsystems'"'"' functionality that can be placed into a subprocessor; and

using the subprocessor to implement an interface between two or more of the subsystems that are placed into the subprocessor.

13. The method of claim 12, further comprising:

analyzing a tradeoff between resource use and a performance criterion; and

attempting to minimize the resource use while not exceeding a predetermined threshold for the performance criterion.

14. The method of claim 13, wherein the performance criterion includes execution speed.

15. The method of claim 13, wherein the performance criterion includes latency.

16. The method of claim 13, wherein the performance criterion includes memory use.

17. The method of claim 13, wherein the resource use includes power consumption.

19. The method of claim 13, wherein the resource use includes space.