Shared interrupt control method and system for a digital signal processor

• US 20070088938A1
• Filed: 10/18/2005
• Published: 04/19/2007
• Est. Priority Date: 10/18/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Anderson, William, Codrescu, Lucian
• Granted Patent: US 7,702,889 B2
• Time in Patent Office: Days
• US Class Current: 712/244
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

Techniques for the design and use of a digital signal processor, including (but not limited to) processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system process interrupts arising in a multithreaded processor by receiving in an interrupt register a plurality of interrupts of a statistically indeterminate interrupt type and then associating a plurality of processing threads with the interrupt register for receiving the interrupt from the interrupt register. The method and system mask at least a subset of the plurality of processing threads so as to receive within each of the threads within the subset only ones of the plurality of interrupts of one or more predetermined types, thereby controlling on a per thread basis the processing of the plurality of interrupts according to the mask associated with a particular thread.

Claims

1. A method for processing interrupts arising in a multithreaded processor, comprising the steps of:

receiving in an interrupt register a plurality of interrupts of a statistically indeterminate interrupt type;

associating a plurality of processing threads with said interrupt register for receiving said interrupt from said interrupt register;

masking at least a subset of said plurality of processing threads so as to receive within each of said threads within said subset only ones of said plurality of interrupts of one or more predetermined types, thereby controlling on a per thread basis the processing of said plurality of interrupts according to the mask associated with a particular thread.

2. The method of claim 1, further comprising the step of masking said at least a subset of said plurality of processing threads using a mask selected from a programmable set of masks corresponding to a predetermined set of interrupt types.

3. The method of claim 1, further comprising the step of processing said interrupt with a processing thread in the event that such processing thread has interrupt processing enabled, and said mask corresponds to the type of said interrupt, and said thread is not an exception handler.

4. The method of claim 1, further comprising the step of determining said interrupt to correspond to a mask using a logical AND of said interrupt within said interrupt register with the contents of a mask register containing said mask and associating with a thread.

5. The method of claim 1, further comprising the step of determining a priority of processing one of said masks within said interrupt register in the event that said interrupt register contains a plurality of said masks.

6. The method of claim 1, further comprising the steps of clearing a received one of said interrupts from said interrupt register in the event that a thread processes said one of said interrupts.

7. The method of claim 6, further comprising the step of disabling said thread processing from said one of said interrupts during the processing of said interrupt.

8. The method of claim 1, further comprising the steps of further comprising the step of nesting said processing of said plurality of interrupts using a plurality of software instructions.

9. The method of claim 1, further comprising the step of receiving at random for processing in any of said plurality of threads any of said interrupts having the property of being non-maskable.

10. A system for operation in association with a digital signal processor for processing interrupts arising in a multithreaded processor, comprising:

an interrupt register associated with said processor for receiving a plurality of interrupts of a statistically indeterminate interrupt type;

thread control circuitry for associating a plurality of processing threads with said interrupt register for receiving said interrupt from said interrupt register; and

a mask register for applying a mask to at least a subset of said plurality of processing threads such that said subset of said plurality of processing threads receives only ones of said plurality of interrupts of one or more predetermined types corresponding to said mask, thereby controlling on a per thread basis the processing of said plurality of interrupts according to the mask and the interrupt type.

11. The system of claim 10, wherein said mask register further comprises circuitry and instructions for masking said at least a subset of said plurality of processing threads using a mask selected from a programmable set of masks corresponding to a predetermined set of interrupt types.

12. The system of claim 10, wherein said processor further comprises processing instructions and circuitry for processing said interrupt with a processing thread in the event that such processing thread has interrupt processing enabled, and said mask corresponds to the type of said interrupt, and said thread is not an exception handler.

13. The system of claim 10, wherein said processor further comprises processing circuitry and instructions for determining said interrupt to correspond to a mask using a logical AND of said interrupt within said interrupt register with the contents of a mask register containing said mask and associating with a thread.

14. The system of claim 10, wherein said processor further comprises processing circuitry and instructions determining a priority of processing one of said masks within said interrupt register in the event that said interrupt register contains a plurality of said masks.

15. The system of claim 10, wherein said interrupt register processor further comprises circuitry and instructions for clearing a received one of said interrupts from said interrupt register in the event that a thread processes said one of said interrupts.

16. The system of claim 15, wherein said processor further comprises circuitry and instructions for disabling said thread from processing said one of said interrupts during the processing of said interrupt.

17. The system of claim 10, wherein said processor further comprises processing instructions for nesting said processing of said plurality of interrupts.

18. The system of claim 10, wherein said processor further comprises processing circuitry and instructions for receiving at random for processing in any of said plurality of threads any of said interrupts having the property of being non-maskable.

19. A digital signal processor for operation in support of a personal electronics device, said digital signal process comprising means for shared control processing means for processing a predetermined set of interrupt types in multi-threaded processing, said shared control processing means comprising:

means for associating an interrupt controller with a plurality of processor pipeline threads

means for receiving a first external interrupt in said interrupt controller, said first external interrupt being of an arbitrary type;

means for associating a first mask with said first external interrupt for enabling a set of said plurality of processor threads to accept said first external interrupt;

means for directing said first external interrupt to a first available processor pipeline thread capable of accepting said first external interrupt and said first mask;

means for receiving a second external interrupt in said interrupt controller, said second external interrupt being of an arbitrary type;

means for associating a second mask with said second external interrupt for enabling a set of said plurality of processor pipeline threads to accept said second external interrupt;

means for directing said second external interrupt to a next available processor pipeline thread capable of accepting said second external interrupt and said second mask;

means for repeating said receiving steps, said associating steps, and said directing steps as external interrupts stream to said interrupt controller for processing by said digital signal processor, thereby providing to each of said set of said plurality of processor pipeline threads a flow of arbitrary external interrupts and associated masks in a distributed flow.

20. The digital signal processor system of claim 19, further comprising means for masking a subset of said plurality of processor threads using a mask selected from a programmable set of masks corresponding to a predetermined set of interrupt types.

21. The digital signal processor system of claim 19, further comprising means for processing said interrupt with a processor thread in the event that such processor thread has interrupt processing enabled, and said mask corresponds to the type of said interrupt, and said thread is not an exception handler.

22. The digital signal processor system of claim 19, further comprising means for determining said interrupt to correspond to a mask using a logical AND of said interrupt within said interrupt register with the contents of a mask register containing said mask and associating with a thread.

23. The digital signal processor system of claim 19, further comprising means determining a priority of processing one of said masks within said interrupt register in the event that said interrupt register contains a plurality of said masks.

24. The digital signal processor system of claim 19, further comprising means for clearing a received one of said interrupts from said interrupt register in the event that a thread processes said one of said interrupts.

25. The digital signal processor system of claim 19, further comprising means for disabling said thread processing from said one of said interrupts during the processing of said interrupt.

26. The digital signal processor system of claim 19, further comprising means for nesting said processing of said plurality of interrupts using a plurality of software instructions.

27. The digital signal processor system of claim 26, further comprising means for receiving at random for processing in any of said plurality of threads any of said interrupts having the property of being non-maskable.

28. A computer usable medium having computer readable program code means embodied therein for processing instructions on digital signal processor, the computer usable medium comprising:

computer readable program code means for receiving in an interrupt register a plurality of interrupts of a statistically indeterminate interrupt type;

computer readable program code means for associating a plurality of processing threads with said interrupt register for receiving said interrupt from said interrupt register;

computer readable program code means for masking at least a subset of said plurality of processing threads so as to receive within each of said threads within said subset only ones of said plurality of interrupts of one or more predetermined types, thereby controlling on a per thread basis the processing of said plurality of interrupts according to the mask associated with a particular thread.

29. The computer usable medium of claim 28, further comprising computer readable program code means for masking said at least a subset of said plurality of processing threads using a mask selected from a programmable set of masks corresponding to a predetermined set of interrupt types.