Data copyright management

• US 20070088960A1
• Filed: 08/29/2006
• Published: 04/19/2007
• Est. Priority Date: 10/27/1994
• Status: Active Grant

• Current Assignee: Piracy Protection LLC (LF Capital Partners, LLC)
• Original Assignee: Intarsia Software LLC (Intellectual Ventures LLC)
• Inventors: Saito, Makoto
• Granted Patent: US 7,986,785 B2
• Time in Patent Office: Days
• US Class Current: 713/193
• CPC Class Codes: G06F 21/109 by using specially-adapted hardware at the client
• CPC Class Codes: G06F 2211/007 Encryption, En-/decode, En-/decipher, En-/decypher, Scramble, (De-)compress
• CPC Class Codes: G06F 2211/008 Public Key, Asymmetric Key, Asymmetric Encryption
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G06Q 20/00 Payment architectures, schemes or protocols apparatus for performing or posting payment transactions G07F7/08, G07F19/00; electronic cash registers G07G1/12
• CPC Class Codes: G06Q 20/02 involving a neutral party, e.g. certification authority, notary or trusted third party [TTP]
• CPC Class Codes: G06Q 20/06 Private payment circuits, e.g. involving electronic currency used among participants of a common payment scheme
• CPC Class Codes: G06Q 20/1235 with control of digital rights management [DRM]
• CPC Class Codes: G06Q 20/363 with the personal data of a user
• CPC Class Codes: G06Q 20/3823 combining multiple encryption tools for a transaction
• CPC Class Codes: G06Q 20/3829 involving key management
• CPC Class Codes: G06T 1/0021 Image watermarking
• CPC Class Codes: G07F 7/0866 by active credit-cards adapted therefor G07F7/1008 takes precedence
• CPC Class Codes: G07F 7/1016 Devices or methods for securing the PIN and other transaction-data, e.g. by encryption arrangements for secret communication, see H04L9/00
• CPC Class Codes: H04L 63/0442 wherein the sending and receiving network entities apply asymmetric encryption, i.e. different keys for encryption and decryption cryptographic mechanisms or cryptographic arrangements for public-key encryption H04L9/30
• CPC Class Codes: H04L 63/0464 using hop-by-hop encryption, i.e. wherein an intermediate entity decrypts the information and re-encrypts it before forwarding it
• CPC Class Codes: H04L 63/062 for key distribution, e.g. centrally by trusted party cryptographic mechanisms or cryptographic arrangements for key distribution involving a central third party H04L9/0819
• CPC Class Codes: H04L 63/126 the source of the received data
• CPC Class Codes: H04N 21/2347 involving video stream encryption
• CPC Class Codes: H04N 21/2541 Rights Management protecting software against unauthorised usage in a vending or licensing environment G06F21/10; security in data switching network management H04L41/28; security management or policies for network security H04L63/20; access security in wireless networks H04W12/08
• CPC Class Codes: H04N 21/4181 : for conditional access
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4334 : Recording operations recording of a television signal H04N5/76; arrangements for recording or accumulating broadcast information or broadcast-related information H04H60/27
• CPC Class Codes: H04N 21/4405 : involving video stream decryption
• CPC Class Codes: H04N 21/4408 : involving video stream encryption, e.g. re-encrypting a decrypted video stream for redistribution in a home network
• CPC Class Codes: H04N 21/4623 : Processing of entitlement messages, e.g. ECM [Entitlement Control Message] or EMM [Entitlement Management Message] arrangements for conditional access to broadcast information or to broadcast-related services H04H60/14
• CPC Class Codes: H04N 21/4627 : Rights management associated to the content security in data switching network management H04L41/28; security management or policies for network security H04L63/20; access security in wireless networks H04W12/08
• CPC Class Codes: H04N 21/835 : Generation of protective data, e.g. certificates protecting software against unauthorised usage in a vending or licensing environment G06F21/10
• CPC Class Codes: H04N 7/1675 : Providing digital key or authorisation information for generation or regeneration of the scrambling sequence pseudo-random number generators in general G06F7/58

Abstract

Embodiments of methods, apparatuses, devices, and/or systems for data copyright management are described.

Claims

1-21. -21. (canceled)

22. A method, comprising:

decrypting encrypted copyrighted digital data;

reencrypting said copyrighted digital data thus decrypted; and

storing, copying, and/or transferring, or combinations thereof, said copyrighted digital data only after reencrypting said copyrighted digital data.

23. A method according to claim 22, wherein said decrypting or reencrypting are performed within a device comprising one or more of the following:

an IC, an IC card, a PC card, and/or an insertion board, or combinations thereof.

24. A method according to claim 22, wherein said decrypting and said reencrypting are performed at the same time for at least a partial duration.

25. A method according to claim 22, wherein said decrypting is performed via a first processor, said reencrypting is performed via a second processor, and wherein said decrypting and said reencrypting are performed at the same time for at least a partial duration.

26. A method according to claim 22, wherein said decrypting is performed with a first crypt key, and wherein said reencrypting is performed with a second crypt key.

27. A method according to claim 22, wherein said decrypting is performed with a first crypt key, wherein said reencrypting is performed with a second crypt key, wherein one or more of said first crypt key and/or said second crypt key comprise a use permit key, wherein said use permit key comprises one or more of the following forms of usage:

view permit, store permit, copy permit, edit permit, and/or transfer permit, or combinations thereof.

28. A method according to claim 22, further comprising attaching one or more of the following to said copyrighted digital data:

copyright information as a copyright information label and/or a digital signature, or combinations thereof.

29. An article comprising:

a storage medium having stored thereon instructions, that, if executed, result in;

decrypting encrypted copyrighted digital data;

encrypting said copyrighted digital data thus decrypted; and

storing, copying, and/or transferring, or combinations thereof, said copyrighted digital data only after reencrypting said copyrighted digital data.

30. The article according to claim 29, wherein said decrypting or reencrypting are performed within a device comprising one or more of the following:

an IC. an IC card, a PC card, and/or an insertion board, or combinations thereof.

31. The article according to claim 29, wherein said decrypting and said reencrypting are performed at the same time for at least a partial duration.

32. The article according to claim 29, wherein said decrypting is performed via a first processor, said reencrypting is performed via a second processor, and wherein said decrypting and said reencrypting are performed at the same time for at least a partial duration.

33. The article according to claim 29, wherein said decrypting is performed with a first crypt key, and wherein said reencrypting is performed with a second crypt key.

34. The article according to claim 29, wherein said decrypting is performed with a first crypt key, wherein said reencrypting is performed with a second crypt key, wherein one or more of said first crypt key and/or said second crypt key comprise a use permit key, wherein said use permit key comprises one or more of the following forms of usage:

view permit, store permit, copy permit, edit permit, and/or transfer permit, or combinations thereof.

35. The article according to claim 29, further comprising attaching one or more of the following to said copyrighted digital data:

copyright information as a copyright information label and/or a digital signature, or combinations thereof.

36. An apparatus, comprising:

means for decrypting encrypted copyrighted digital data;

means for reencrypting said copyrighted digital data thus decrypted; and

means for storing, copying, and/or transferring, or combinations thereof, said copyrighted digital data only after said means for reencrypting said copyrighted digital data reencrypts said copyrighted digital data.

37. The apparatus according to claim 36, wherein one or more of said means for decrypting and/or said means for reencrypting comprise at least a portion of one or more of the following:

an IC. an IC card, a PC card, and/or an insertion board, or combinations thereof.

38. The apparatus according to claim 36, wherein said means for decrypting and said means for reencrypting operate at the same time for at least a partial duration.

39. The apparatus according to claim 36, wherein said means for decrypting utilizes a first crypt key, and wherein said means for reencrypting utilizes a second crypt key.

40. The apparatus according to claim 36, wherein said means for decrypting utilizes a first crypt key, wherein said means for reencrypting utilizes a second crypt key, wherein one or more of said first crypt key and/or said second crypt key comprise a use permit key, wherein said use permit key comprises one or more of the following forms of usage:

view permit, store permit, copy permit, edit permit, and/or transfer permit, or combinations thereof.

41. The apparatus according to claim 36, further comprising means for attaching one or more of the following to said copyrighted digital data:

copyright information as a copyright information label and/or a digital signature, or combinations thereof.

42. The apparatus according to claim 36, further comprising one or more means for displaying, processing, and/or editing said decrypted copyrighted digital data.

43. A system, comprising:

one or more processors capable of decrypting encrypted copyrighted digital data and capable of reencrypting said copyrighted digital data; and

wherein said system is capable storing, copying, and/or transferring, or combinations thereof, said copyrighted digital data only after said one or more processors reencrypt said digital cash data.

44. The system according to claim 43, wherein one or more of said first processor and said second processor comprise at least a portion of one or more of the following:

an IC, an IC card, a PC card, and/or an insertion board, or combinations thereof.

45. The system according to claim 43, wherein said one or more processors are further capable of decrypting encrypted copyrighted digital data and reencrypting copyrighted digital data at the same time for at least a partial duration.

46. The system according to claim 43, wherein said one or more processors are further capable of decrypting with a first crypt key and reencrypting with a second crypt key.

47. The system according to claim 43, wherein said one or more processors are further capable of decrypting with a first crypt key and reencrypting with a second crypt key, and wherein one or more of said first crypt key and/or said second crypt key comprise a use permit key, wherein said use permit key comprises one or more of the following forms of usage:

view permit, store permit, copy permit, edit permit, and/or transfer permit, or combinations thereof.

48. The system according to claim 43, wherein said one or more processors are further capable of attaching one or more of the following to said copyrighted digital data:

copyright information as a copyright information label and/or a digital signature, or combinations thereof.

49. The system according to claim 43, wherein said one or more processors comprise:

a first processor capable of decrypting encrypted copyrighted digital data; and

second processor capable of reencrypting said copyrighted digital data.

50. The system according to claim 43, further comprising:

a central processing unit type bus, wherein said central processing unit type bus is capable of being connected to a system type bus of a user terminal;

a read-only type memory, an electrically erasable programmable type memory, and a read/write type memory connected to said central processing unit type bus; and

wherein one of said one or more processors comprise a central processing unit connected to said central processing unit type bus.

51. The system according to claim 43, further comprising:

a central processing unit type bus, wherein said central processing unit type bus is capable of being connected to a system type bus of a user terminal;

a read-only type memory, an electrically erasable programmable type memory, and a read/write type memory connected to said central processing unit type bus;

wherein one of said one or more processors comprise a central processing unit connected to said central processing unit type bus;

a data copyright management system program, a copyright management program, crypt algorithm and user information stored in said read-only type memory; and

wherein one or more crypt keys are stored in said electrically erasable programmable type memory.

52. The system according to claim 43, further comprising:

a central processing unit type bus, wherein said central processing unit type bus is capable of being connected to a system type bus of a user terminal;

a read-only type memory, an electrically erasable programmable type memory, and a read/write type memory connected to said central processing unit type bus;

wherein one of said one or more processors comprise a central processing unit connected to said central processing unit type bus; and

wherein said central processing unit type bus is capable of being connected to a system type bus of a user terminal via a bus comprises one or more of the following;

a PCI type bus, and/or a SCSI type bus, or combinations thereof.

53. The system according to claim 43, further comprising:

a first central processing unit type bus, wherein said first central processing unit type bus is capable of being connected to a system type bus of a user terminal;

a first read-only type memory, a first electrically erasable programmable type memory, and a first read/write type memory connected to said first central processing unit type bus;

wherein one of said one or more processors comprises a first central processing unit connected to said first central processing unit type bus;

a second central processing unit type bus, wherein said second central processing unit type bus is capable of being connected to the system type bus of user terminal;

a second read-only type memory, a second electrically erasable programmable type memory, and a second read/write type memory connected to said second central processing unit type bus; and

wherein one of said one or more processors comprises a second central processing unit connected to said second central processing unit type bus.

54. The system according to claim 43, further comprising:

a central processing unit type bus, wherein said central processing unit type bus is capable of being connected to a system type bus of a user terminal;

a read-only type memory, an electrically erasable programmable type memory, and a read/write type memory connected to said central processing unit type bus;

a communications device and a CD-ROM type drive connected to said central processing unit type bus; and

wherein one of said one or more processors comprises a central processing unit connected to said central processing unit type bus.

55. The system according to claim 43, further comprising:

a first central processing unit type bus, wherein said first central processing unit type bus is capable of being connected to a system type bus of a user terminal;

a first read-only type memory, a first electrically erasable programmable type memory, and a first read/write type memory connected to said first central processing unit type bus;

a communications device and a CD-ROM type drive connected to said first central processing unit type bus;

wherein one of said one or more processors comprise a first central processing unit connected to said first central processing unit type bus;

a second central processing unit type bus, wherein said second central processing unit type bus is capable of being connected to system type bus of user terminal;

a second read-only type memory, a second electrically erasable programmable type memory, and a second read/write type memory connected to said second central processing unit type bus; and

wherein one of said one or more processors comprise a second central processing unit connected to said second central processing unit type bus.